EPM9320LI84-20N vs EPM9320LC84-20N Vergleich
Detaillierter Direktvergleich von EPM9320LI84-20N von Altera und EPM9320LC84-20N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9320LI84-20N | EPM9320LC84-20N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $9,75 | $10,25 |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 to 12,000 | 6,000 |
| User I/O Pins | 60 | — |
| Total Pins | 84 | — |
| Gehäuse | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) | — |
| Propagation Delay (tPD) | 20 ns (speed grade -20) | 16 ns |
| Pin-to-Pin Delay | 16 ns (per DigChip spec block) | — |
| Maximum Counter Frequency | 118 MHz | — |
| Logic Family | CMOS, EEPROM-based | CMOS (EEPROM-based) |
| Versorgungsspannung | 5.0 V | — |
| Betriebstemperatur | 0 C to +70 C (commercial) | 0 C to +70 C (Commercial) |
| Programming Interface | IEEE 1149.1 JTAG, in-system programmable | — |
| Architecture | Multiple Array MatriX (MAX) - third generation | — |
| Process Technology | Advanced CMOS EEPROM | — |
| RoHS-Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Series | — | MAX 9000 |
| User I/Os | — | 60 |
| Anzahl der Pins | — | 84 |
| Package Type | — | Plastic Leaded Chip Carrier (PLCC-84, J-bend) |
| Package Code | — | QCCJ |
| Internal Frequency | — | 118 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Programming | — | 5.0-V In-System Programmable via JTAG (IEEE 1149.1) |
| Montageart | — | Surface Mount (J-bend) |
| Terminal Form | — | J BEND |
| MSL-Level | — | [DATA_NEEDED: MSL moisture sensitivity level] |