EPM9320LI84-20N vs EPM9320LC84-20N Comparison
Detailed side-by-side comparison of EPM9320LI84-20N by Altera and EPM9320LC84-20N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320LI84-20N | EPM9320LC84-20N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.75 | $10.25 |
| Family | MAX 9000 | β |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| Usable Gates | 6,000 to 12,000 | 6,000 |
| User I/O Pins | 60 | β |
| Total Pins | 84 | β |
| Package | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) | β |
| Propagation Delay (tPD) | 20 ns (speed grade -20) | 16 ns |
| Pin-to-Pin Delay | 16 ns (per DigChip spec block) | β |
| Maximum Counter Frequency | 118 MHz | β |
| Logic Family | CMOS, EEPROM-based | CMOS (EEPROM-based) |
| Supply Voltage | 5.0 V | β |
| Operating Temperature | 0 C to +70 C (commercial) | 0 C to +70 C (Commercial) |
| Programming Interface | IEEE 1149.1 JTAG, in-system programmable | β |
| Architecture | Multiple Array MatriX (MAX) - third generation | β |
| Process Technology | Advanced CMOS EEPROM | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Series | β | MAX 9000 |
| User I/Os | β | 60 |
| Number of Pins | β | 84 |
| Package Type | β | Plastic Leaded Chip Carrier (PLCC-84, J-bend) |
| Package Code | β | QCCJ |
| Internal Frequency | β | 118 MHz |
| Supply Voltage (VCC) | β | 5 V |
| Programming | β | 5.0-V In-System Programmable via JTAG (IEEE 1149.1) |
| Mounting Type | β | Surface Mount (J-bend) |
| Terminal Form | β | J BEND |
| MSL Level | β | [DATA_NEEDED: MSL moisture sensitivity level] |