EPM9320RC208-10 vs EPM9320RC208-15 Vergleich
Detaillierter Direktvergleich von EPM9320RC208-10 von Altera und EPM9320RC208-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9320RC208-10 | EPM9320RC208-15 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $26,40 | $0,00 |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 6,000 | 6,000 |
| Macrocells | 320 | — |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | — |
| Gehäuse | 208-pin RQFP (RC) | 208-pin RQFP (Power QFP) |
| Betriebstemperatur | Commercial (0C to +70C) - 'C' suffix | [DATA_NEEDED: operating temperature range] |
| Versorgungsspannung | 5 V | 5.0 V |
| Speed Grade | -10 | — |
| Programming Interface | JTAG (ByteBlaster/BitBlaster) | — |
| Non-volatile Configuration | Yes (EPROM/EEPROM based) | — |
| Design Tool Support | MAX+PLUS II, Quartus (legacy) | — |
| RoHS-Status | ROHS3 Compliant (per fpgalink listing) | [DATA_NEEDED: RoHS status] |
| Feuchtigkeitsempfindlichkeitsgrad (MSL) | 3 (168 Hours) | — |
| Lead Time | 1-7 days (per fpgalink listing) | — |
| Device Family | — | MAX 9000 |
| Macro Cells | — | 320 |
| Pin-to-Pin Propagation Delay | — | 15 ns (speed grade -15) |
| Maximale Taktfrequenz | — | 117.6 MHz |
| Configuration Technology | — | EEPROM-based (non-volatile) |
| In-System Programmability | — | Yes (ISP via JTAG) |
| JTAG Interface | — | IEEE Std. 1149.1 |
| Package Type | — | 208-BFQFP Exposed Pad |
| Montageart | — | Surface Mount |
| Number of I/O Pins | — | [DATA_NEEDED: user I/O count] |
| Logic Array Blocks | — | [DATA_NEEDED: LAB count] |
| Lebenszyklusstatus | — | Obsolete (PDN0706, 2007) |