EPM9320RC208-15 vs EPM9320RC208-15N Vergleich
Detaillierter Direktvergleich von EPM9320RC208-15 von Altera und EPM9320RC208-15N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9320RC208-15 | EPM9320RC208-15N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $0,00 |
| Device Family | MAX 9000 | — |
| Macro Cells | 320 | 320 |
| Usable Gates | 6,000 | 6,000 |
| Pin-to-Pin Propagation Delay | 15 ns (speed grade -15) | — |
| Maximale Taktfrequenz | 117.6 MHz | 117.6 MHz |
| Versorgungsspannung | 5.0 V | 5.0 V |
| Configuration Technology | EEPROM-based (non-volatile) | CMOS EEPROM (non-volatile) |
| In-System Programmability | Yes (ISP via JTAG) | Yes, via IEEE Std. 1149.1 JTAG |
| JTAG Interface | IEEE Std. 1149.1 | — |
| Gehäuse | 208-pin RQFP (Power QFP) | 208-pin RQFP (PowerQuad Flat Pack) |
| Package Type | 208-BFQFP Exposed Pad | — |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | [DATA_NEEDED: operating temperature range] | — |
| Number of I/O Pins | [DATA_NEEDED: user I/O count] | — |
| Logic Array Blocks | [DATA_NEEDED: LAB count] | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lebenszyklusstatus | Obsolete (PDN0706, 2007) | — |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Flip-Flops | — | 484 |
| Configurable I/O Lines | — | 128 |
| Propagation Delay (tPD) | — | 15 ns |
| I/O Voltage Compatibility | — | 3.3 V or 5 V |
| Terminal Pitch | — | 0.5 mm |
| Betriebstemperaturbereich | — | 0C to +70C (commercial) |
| Packaging | — | Tray |