EPM9400LC84-15 vs EPM9320LC84-15 Vergleich
Detaillierter Direktvergleich von EPM9400LC84-15 von Altera und EPM9320LC84-15 von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9400LC84-15 | EPM9320LC84-15 |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $23,10 | $17,95 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 8,000 | 6,000 |
| Macro Cells | 400 | — |
| Logic Array Blocks | 25 | — |
| Maximum User I/Os | 59 | — |
| Maximum Operating Frequency | 117.6 MHz | — |
| Speed Grade | -15 (15 ns pin-to-pin delay) | — |
| Core Supply Voltage (VCCINT) | 5.0 V | — |
| Input Logic Compatibility | TTL, 3.3 V and 5.0 V tolerant | — |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) | — |
| JTAG Interface | IEEE Std. 1149.1 compliant (ISP) | IEEE Std. 1149.1 boundary-scan compliant |
| Gehäuse | 84-pin PLCC | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Montageart | Surface Mount | Surface Mount |
| Betriebstemperatur | 0C to +70C (Commercial) | -40C to +85C (commercial) [DATA_NEEDED: exact grade] |
| Minimum VCCINT | 4.75 V | — |
| Programming Method | In-System Programmable via JTAG | — |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: confirm from manufacturer] |
| Series | — | EPM9320 |
| Macrocells | — | 320 |
| Logic Array Blocks (LABs) | — | 20 |
| Propagation Delay (tPD) | — | 15 ns (max) |
| Maximale Taktfrequenz | — | 117.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5.0 V nominal) |
| Programmability | — | 5.0 V in-system programmable (ISP) via JTAG |
| Technology | — | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) |
| Built-in Pull-up Resistors | — | Yes, on every I/O pin |
| Architecture Feature | — | Pin-locking across design iterations |