EPM9400LC84-15 vs EPM9320LC84-15 对比

详细并排对比 EPM9400LC84-15 出自 Altera 和 EPM9320LC84-15 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9400LC84-15 EPM9320LC84-15
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $23.10 $17.95
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Usable Gates 8,000 6,000
Macro Cells 400 —
Logic Array Blocks 25 —
Maximum User I/Os 59 —
Maximum Operating Frequency 117.6 MHz —
Speed Grade -15 (15 ns pin-to-pin delay) —
Core Supply Voltage (VCCINT) 5.0 V —
Input Logic Compatibility TTL, 3.3 V and 5.0 V tolerant —
Configuration Memory EEPROM (non-volatile, in-system programmable) —
JTAG Interface IEEE Std. 1149.1 compliant (ISP) IEEE Std. 1149.1 boundary-scan compliant
封装 84-pin PLCC 84-pin PLCC (Plastic Leaded Chip Carrier)
安装类型 Surface Mount Surface Mount
工作温度 0C to +70C (Commercial) -40C to +85C (commercial) [DATA_NEEDED: exact grade]
Minimum VCCINT 4.75 V —
Programming Method In-System Programmable via JTAG —
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: confirm from manufacturer]
Series — EPM9320
Macrocells — 320
Logic Array Blocks (LABs) — 20
Propagation Delay (tPD) — 15 ns (max)
最大时钟频率 — 117.6 MHz
Supply Voltage (VCC) — 4.75 V to 5.25 V (5.0 V nominal)
Programmability — 5.0 V in-system programmable (ISP) via JTAG
Technology — CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX)
Built-in Pull-up Resistors — Yes, on every I/O pin
Architecture Feature — Pin-locking across design iterations

数据手册与资源

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