EPM9400LC84-15 vs EPM9320LC84-15 비교

다음의 상세 나란히 비교: EPM9400LC84-15 제조: Altera 및 EPM9320LC84-15 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM9400LC84-15 EPM9320LC84-15
브랜드 Altera Intel
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete Obsolete
재고 상태 In Stock In Stock
단가 (USD) $23.10 $17.95
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Usable Gates 8,000 6,000
Macro Cells 400 —
Logic Array Blocks 25 —
Maximum User I/Os 59 —
Maximum Operating Frequency 117.6 MHz —
Speed Grade -15 (15 ns pin-to-pin delay) —
Core Supply Voltage (VCCINT) 5.0 V —
Input Logic Compatibility TTL, 3.3 V and 5.0 V tolerant —
Configuration Memory EEPROM (non-volatile, in-system programmable) —
JTAG Interface IEEE Std. 1149.1 compliant (ISP) IEEE Std. 1149.1 boundary-scan compliant
패키지 84-pin PLCC 84-pin PLCC (Plastic Leaded Chip Carrier)
실장 유형 Surface Mount Surface Mount
동작 온도 0C to +70C (Commercial) -40C to +85C (commercial) [DATA_NEEDED: exact grade]
Minimum VCCINT 4.75 V —
Programming Method In-System Programmable via JTAG —
RoHS 상태 [DATA_NEEDED: RoHS status] [DATA_NEEDED: confirm from manufacturer]
Series — EPM9320
Macrocells — 320
Logic Array Blocks (LABs) — 20
Propagation Delay (tPD) — 15 ns (max)
최대 클록 주파수 — 117.6 MHz
Supply Voltage (VCC) — 4.75 V to 5.25 V (5.0 V nominal)
Programmability — 5.0 V in-system programmable (ISP) via JTAG
Technology — CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX)
Built-in Pull-up Resistors — Yes, on every I/O pin
Architecture Feature — Pin-locking across design iterations

데이터시트 & 자료

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