EPM9560ARC240-10N vs EPM9560GC280-15 Vergleich
Detaillierter Direktvergleich von EPM9560ARC240-10N von Altera und EPM9560GC280-15 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM9560ARC240-10N - MAX 9000 CPLD 560 Macro 191 IOs | Altera/Intel
EPM9560ARC240-10N ObsoleteAltera
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 ObsoleteSpezifikationsvergleich
| Parameter | EPM9560ARC240-10N | EPM9560GC280-15 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $19,50 | $115,00 |
| Logic Family | MAX 9000 (CPLD) | — |
| Process Technology | CMOS EEPROM | — |
| Macro Cells | 560 | 560 |
| User I/Os | 191 | — |
| Logic Array Blocks (LABs) | 16 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Internal Frequency (fMAX) | 145 MHz | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| Betriebstemperatur | 0°C to +70°C (Commercial) | — |
| Gehäuse | 240-pin RQFP (32x32 mm) | — |
| Montageart | Surface Mount | Through-Hole |
| Programming Interface | IEEE 1149.1 JTAG / ByteBlaster | — |
| Programmability | In-system, EEPROM-based (non-volatile) | In-System Programmable (ISP) via JTAG IEEE 1149.1 |
| I/O Standard | 5.0 V TTL-compatible | — |
| RoHS-Status | Non-RoHS (legacy Altera part) | Non-compliant (ceramic CPGA, contains lead) |
| Family | MAX 9000 | MAX 9000 |
| Device Type | — | EE PLD (CMOS EEPROM-based CPLD) |
| Typical Gates | — | 12,000 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Propagation Delay (tpd) | — | 15 ns (speed grade -15) |
| Propagation Delay (alternate datasheet figure) | — | 16.6 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| Operating Temperature (Commercial) | — | 0C to +70C |
| Package Type | — | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Technology | — | CMOS EEPROM, 0.5 um process (MAX third-gen) |
| Architecture | — | Multiple Array MatriX (MAX) |
| Lebenszyklusstatus | — | Obsolete (legacy Altera MAX 9000 family) |