EPM9560ARC240-10N vs EPM9560GC280-15 Comparison

Detailed side-by-side comparison of EPM9560ARC240-10N by Altera and EPM9560GC280-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560ARC240-10N EPM9560GC280-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Logic Family MAX 9000 (CPLD) —
Process Technology CMOS EEPROM —
Macro Cells 560 560
User I/Os 191 —
Logic Array Blocks (LABs) 16 —
Propagation Delay (tPD) 10 ns —
Internal Frequency (fMAX) 145 MHz —
Supply Voltage (VCCINT) 5.0 V —
Operating Temperature 0°C to +70°C (Commercial) —
Package 240-pin RQFP (32x32 mm) —
Mounting Type Surface Mount Through-Hole
Programming Interface IEEE 1149.1 JTAG / ByteBlaster —
Programmability In-system, EEPROM-based (non-volatile) In-System Programmable (ISP) via JTAG IEEE 1149.1
I/O Standard 5.0 V TTL-compatible —
RoHS Status Non-RoHS (legacy Altera part) Non-compliant (ceramic CPGA, contains lead)
Family MAX 9000 MAX 9000
Device Type — EE PLD (CMOS EEPROM-based CPLD)
Typical Gates — 12,000
Maximum Operating Frequency — 117.6 MHz
Propagation Delay (tpd) — 15 ns (speed grade -15)
Propagation Delay (alternate datasheet figure) — 16.6 ns
Supply Voltage (VCCINT/VCCIO) — 5.0 V
Operating Temperature (Commercial) — 0C to +70C
Package Type — CPGA-280 (Ceramic Pin Grid Array, 280 pins)
Technology — CMOS EEPROM, 0.5 um process (MAX third-gen)
Architecture — Multiple Array MatriX (MAX)
Lifecycle Status — Obsolete (legacy Altera MAX 9000 family)

Datasheets & Resources

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