EPM9560ARC240-10N vs EPM9560GC280-15 对比

详细并排对比 EPM9560ARC240-10N 出自 Altera 和 EPM9560GC280-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560ARC240-10N EPM9560GC280-15
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $19.50 $115.00
Logic Family MAX 9000 (CPLD) —
Process Technology CMOS EEPROM —
Macro Cells 560 560
User I/Os 191 —
Logic Array Blocks (LABs) 16 —
Propagation Delay (tPD) 10 ns —
Internal Frequency (fMAX) 145 MHz —
Supply Voltage (VCCINT) 5.0 V —
工作温度 0°C to +70°C (Commercial) —
封装 240-pin RQFP (32x32 mm) —
安装类型 Surface Mount Through-Hole
Programming Interface IEEE 1149.1 JTAG / ByteBlaster —
Programmability In-system, EEPROM-based (non-volatile) In-System Programmable (ISP) via JTAG IEEE 1149.1
I/O Standard 5.0 V TTL-compatible —
RoHS 状态 Non-RoHS (legacy Altera part) Non-compliant (ceramic CPGA, contains lead)
Family MAX 9000 MAX 9000
Device Type — EE PLD (CMOS EEPROM-based CPLD)
Typical Gates — 12,000
Maximum Operating Frequency — 117.6 MHz
Propagation Delay (tpd) — 15 ns (speed grade -15)
Propagation Delay (alternate datasheet figure) — 16.6 ns
Supply Voltage (VCCINT/VCCIO) — 5.0 V
Operating Temperature (Commercial) — 0C to +70C
Package Type — CPGA-280 (Ceramic Pin Grid Array, 280 pins)
Technology — CMOS EEPROM, 0.5 um process (MAX third-gen)
Architecture — Multiple Array MatriX (MAX)
生命周期状态 — Obsolete (legacy Altera MAX 9000 family)

数据手册与资源

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