EPM9560WC208-15 vs EPM9560WC208 Vergleich
Detaillierter Direktvergleich von EPM9560WC208-15 von Altera und EPM9560WC208 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM9560WC208-15 | EPM9560WC208 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | NRND |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $105,00 | $125,00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EE PLD (Electrically Erasable Programmable Logic Device) | EE Programmable Logic Device (CPLD) |
| Technology | CMOS | — |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 35 | 35 |
| Flip-Flops | 772 | 772 |
| User I/O Pins (max) | 149 | — |
| Maximale Taktfrequenz | 117.6 MHz | 117.6 MHz |
| Propagation Delay (tPD) | 16.6 ns | — |
| Speed Grade | -15 | — |
| Supply Voltage - I/O | 3.3 V or 5.0 V (configurable) | — |
| Gehäuse | 208-pin CQFP (Ceramic Quad Flat Pack) | 208-pin CQFP (Ceramic Quad Flat Pack) |
| Terminal Pitch | 0.50 mm | 0.50 mm |
| Montageart | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1 boundary scan) | IEEE 1149.1 JTAG |
| RoHS-Status | RoHS3 Compliant (per third-party listings) | [DATA_NEEDED: RoHS compliance] |
| Maximum User I/O | — | 149 |
| Propagation Delay (tpd, -15 grade) | — | 16.6 ns |
| Versorgungsspannung | — | 3.3 V or 5 V |
| Process Technology | — | CMOS, electrically erasable |
| Configuration Memory | — | Non-volatile EE (instant-on) |
| Hot Socketing Support | — | Yes |
| MSL-Level | — | [DATA_NEEDED: MSL level] |