EPM9560WC208-15 vs EPM9560WC208 Comparison
Detailed side-by-side comparison of EPM9560WC208-15 by Altera and EPM9560WC208 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560WC208-15
EPM9560WC208-15 - 560-Macrocell EE PLD, 117.6 MHz | Altera
EPM9560WC208-15 ObsoleteAltera
EPM9560WC208
EPM9560WC208 - 560 Macrocell EE PLD MAX 9000 | Altera | CQFP-208
EPM9560WC208 NrndSpecification Comparison
| Parameter | EPM9560WC208-15 | EPM9560WC208 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $105.00 | $125.00 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EE PLD (Electrically Erasable Programmable Logic Device) | EE Programmable Logic Device (CPLD) |
| Technology | CMOS | β |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 35 | 35 |
| Flip-Flops | 772 | 772 |
| User I/O Pins (max) | 149 | β |
| Maximum Clock Frequency | 117.6 MHz | 117.6 MHz |
| Propagation Delay (tPD) | 16.6 ns | β |
| Speed Grade | -15 | β |
| Supply Voltage - I/O | 3.3 V or 5.0 V (configurable) | β |
| Package | 208-pin CQFP (Ceramic Quad Flat Pack) | 208-pin CQFP (Ceramic Quad Flat Pack) |
| Terminal Pitch | 0.50 mm | 0.50 mm |
| Mounting Type | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1 boundary scan) | IEEE 1149.1 JTAG |
| RoHS Status | RoHS3 Compliant (per third-party listings) | [DATA_NEEDED: RoHS compliance] |
| Maximum User I/O | β | 149 |
| Propagation Delay (tpd, -15 grade) | β | 16.6 ns |
| Supply Voltage | β | 3.3 V or 5 V |
| Process Technology | β | CMOS, electrically erasable |
| Configuration Memory | β | Non-volatile EE (instant-on) |
| Hot Socketing Support | β | Yes |
| MSL Level | β | [DATA_NEEDED: MSL level] |