MM74C949N vs ADC0809CCN Vergleich
Detaillierter Direktvergleich von MM74C949N von Texas Instruments und ADC0809CCN von Texas Instruments. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | MM74C949N | ADC0809CCN |
|---|---|---|
| Marke | Texas Instruments | Texas Instruments |
| Kategorie | ADC/DAC | ADC/DAC |
| Lebenszyklusstatus | Obsolete | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $3,65 | $3,40 |
| Auflösung | 8 bits | 8 bits |
| Number of Input Channels | 8 (single-ended, multiplexed) | — |
| Conversion Architecture | Successive Approximation (SAR) | — |
| Conversion Time | 116 microseconds (typical) | — |
| Versorgungsspannung | 5 V (single supply) | — |
| Analog Input Type | Single-ended, 8-channel MUX | — |
| Digital Interface | 8-bit microprocessor-compatible, tri-state outputs | — |
| Gehäuse | 28-PDIP (Plastic DIP, 28-pin) | 28-pin PDIP (through-hole) |
| Betriebstemperaturbereich | -40 C to +85 C | — |
| Output Code | Binary (unipolar) | — |
| Technology | CMOS | — |
| Sample-and-Hold | Internal | — |
| Reference | Internal (external reference option [DATA_NEEDED: pin details]) | — |
| RoHS-Status | [DATA_NEEDED: RoHS status - legacy part predates RoHS directive; check distributor listings] | Compliant (NOPB variant); non-compliant legacy |
| Pin-Anzahl | 28 | — |
| Montageart | Through-Hole (DIP) | Through-Hole (DIP) |
| Lebenszyklusstatus | Obsolete / End of Life (per GlobalSpec listing) | — |
| Architecture | — | Successive Approximation (SAR) |
| Number of Channels | — | 8 single-ended |
| Sample Rate (max) | — | 10 kSPS |
| Input Type | — | Single-Ended, Multiplexed |
| Supply Voltage (VCC) | — | 4.5 V to 5.25 V (5 V typical) |
| Versorgungsstrom | — | [DATA_NEEDED: typical quiescent current] |
| Analog Input Voltage Range | — | 0 V to VCC |
| Integral Nonlinearity (INL) | — | ±1 LSB max |
| Differential Nonlinearity (DNL) | — | ±1 LSB max (no missing codes) |
| Conversion Time (typ) | — | [DATA_NEEDED: at fCLK] |
| Clock Frequency | — | 10 kHz to 1.1 MHz |
| Referenzspannung | — | Internal 256R ladder, VREF+ / VREF- pins |
| Digital I/O Logic Level | — | TTL/CMOS compatible |
| Betriebstemperatur | — | -40 °C to +85 °C |
| Output Interface | — | 8-bit parallel, tri-state latched |
| Channel Selection | — | 3-bit address latch (A0/A1/A2) |