MM74C949N vs ADC0809CCN 对比
详细并排对比 MM74C949N 出自 Texas Instruments 和 ADC0809CCN 出自 Texas Instruments。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | MM74C949N | ADC0809CCN |
|---|---|---|
| 品牌 | Texas Instruments | Texas Instruments |
| 分类 | ADC/DAC | ADC/DAC |
| 生命周期状态 | Obsolete | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $3.65 | $3.40 |
| 分辨率 | 8 bits | 8 bits |
| Number of Input Channels | 8 (single-ended, multiplexed) | — |
| Conversion Architecture | Successive Approximation (SAR) | — |
| Conversion Time | 116 microseconds (typical) | — |
| 电源电压 | 5 V (single supply) | — |
| Analog Input Type | Single-ended, 8-channel MUX | — |
| Digital Interface | 8-bit microprocessor-compatible, tri-state outputs | — |
| 封装 | 28-PDIP (Plastic DIP, 28-pin) | 28-pin PDIP (through-hole) |
| 工作温度范围 | -40 C to +85 C | — |
| Output Code | Binary (unipolar) | — |
| Technology | CMOS | — |
| Sample-and-Hold | Internal | — |
| Reference | Internal (external reference option [DATA_NEEDED: pin details]) | — |
| RoHS 状态 | [DATA_NEEDED: RoHS status - legacy part predates RoHS directive; check distributor listings] | Compliant (NOPB variant); non-compliant legacy |
| 引脚数量 | 28 | — |
| 安装类型 | Through-Hole (DIP) | Through-Hole (DIP) |
| 生命周期状态 | Obsolete / End of Life (per GlobalSpec listing) | — |
| Architecture | — | Successive Approximation (SAR) |
| Number of Channels | — | 8 single-ended |
| Sample Rate (max) | — | 10 kSPS |
| Input Type | — | Single-Ended, Multiplexed |
| Supply Voltage (VCC) | — | 4.5 V to 5.25 V (5 V typical) |
| 电源电流 | — | [DATA_NEEDED: typical quiescent current] |
| Analog Input Voltage Range | — | 0 V to VCC |
| Integral Nonlinearity (INL) | — | ±1 LSB max |
| Differential Nonlinearity (DNL) | — | ±1 LSB max (no missing codes) |
| Conversion Time (typ) | — | [DATA_NEEDED: at fCLK] |
| Clock Frequency | — | 10 kHz to 1.1 MHz |
| 基准电压 | — | Internal 256R ladder, VREF+ / VREF- pins |
| Digital I/O Logic Level | — | TTL/CMOS compatible |
| 工作温度 | — | -40 °C to +85 °C |
| Output Interface | — | 8-bit parallel, tri-state latched |
| Channel Selection | — | 3-bit address latch (A0/A1/A2) |