XA3S50-4PQG208Q vs XA3S50-4PQG208I Vergleich

Detaillierter Direktvergleich von XA3S50-4PQG208Q von AMD und XA3S50-4PQG208I von Xilinx. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.

Spezifikationsvergleich

Parameter XA3S50-4PQG208Q XA3S50-4PQG208I
Marke AMD Xilinx
Kategorie FPGA & CPLD FPGA & CPLD
Lebenszyklusstatus Obsolete Aktiv
Device Type Field Programmable Gate Array (FPGA) Spartan-3A automotive field-programmable gate array (FPGA)
FPGA Family Spartan-3 XA —
System Gates 50,000 gates 50,000 gates
Configurable Logic Blocks 192 CLBs 192 CLBs
Logic Cells 1,728 logic cells 1,728 logic elements
Maximum Operating Frequency 125 MHz —
User I/O Pins 124 I/O —
On-Chip RAM 73,728 bits —
Versorgungsspannung 1.2 V —
Maximum Data Transfer Rate per I/O 622 Mb/s —
Single-Ended I/O Standards 17 standards 17 standards
Differential I/O Standards 7 standards 7 standards, including LVDS
Differential I/O Support LVDS —
On-Chip Termination Digitally Controlled —
Gehäuse 208-pin PQFP 208-pin PQFP plastic quad flat package
Package Pin Pitch 0.50 mm —
Terminal Form Gull wing —
Package Shape Square —
Automotive Qualification AEC-Q100 qualified AEC-Q100 automotive-grade designation reported in verified source data
Betriebstemperaturbereich [DATA_NEEDED: operating temperature range] —
Configuration Memory [DATA_NEEDED: configuration memory type] —
Static Power [DATA_NEEDED: static power] —
Dynamic Power [DATA_NEEDED: dynamic power] —
Total RAM Bits — 73,728 bits
User I/O — 124 I/O
Maximum Data Rate per I/O — 622 Mb/s
Core Supply Voltage — 1.2 V
I/O Supply Voltage — 3.3 V
FPGA Technology — 90 nm
Total Package Pins — 208 pins
Speed Grade — -4
Temperature Grade — Industrial, -40°C to +100°C
Digital Termination — Digitally controlled termination supported

Datenblätter & Ressourcen

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