XA3S50-4PQG208Q vs XA3S50-4PQG208I 比較

詳細並排比較 XA3S50-4PQG208Q 由 AMD 與 XA3S50-4PQG208I 由 Xilinx. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。

AMD

XA3S50-4PQG208Q - 125 MHz Spartan-3 XA FPGA | AMD

XA3S50-4PQG208Q Obsolete

Xilinx

XA3S50-4PQG208I ✓ 啟用中

參數	XA3S50-4PQG208Q	XA3S50-4PQG208I
品牌	AMD	Xilinx
類別	FPGA & CPLD	FPGA & CPLD
生命週期狀態	Obsolete	啟用中
Device Type	Field Programmable Gate Array (FPGA)	Spartan-3A automotive field-programmable gate array (FPGA)
FPGA Family	Spartan-3 XA	—
System Gates	50,000 gates	50,000 gates
Configurable Logic Blocks	192 CLBs	192 CLBs
Logic Cells	1,728 logic cells	1,728 logic elements
Maximum Operating Frequency	125 MHz	—
User I/O Pins	124 I/O	—
On-Chip RAM	73,728 bits	—
供應電壓	1.2 V	—
Maximum Data Transfer Rate per I/O	622 Mb/s	—
Single-Ended I/O Standards	17 standards	17 standards
Differential I/O Standards	7 standards	7 standards, including LVDS
Differential I/O Support	LVDS	—
On-Chip Termination	Digitally Controlled	—
封裝	208-pin PQFP	208-pin PQFP plastic quad flat package
Package Pin Pitch	0.50 mm	—
Terminal Form	Gull wing	—
Package Shape	Square	—
Automotive Qualification	AEC-Q100 qualified	AEC-Q100 automotive-grade designation reported in verified source data
工作溫度範圍	[DATA_NEEDED: operating temperature range]	—
Configuration Memory	[DATA_NEEDED: configuration memory type]	—
Static Power	[DATA_NEEDED: static power]	—
Dynamic Power	[DATA_NEEDED: dynamic power]	—
Total RAM Bits	—	73,728 bits
User I/O	—	124 I/O
Maximum Data Rate per I/O	—	622 Mb/s
Core Supply Voltage	—	1.2 V
I/O Supply Voltage	—	3.3 V
FPGA Technology	—	90 nm
Total Package Pins	—	208 pins
Speed Grade	—	-4
Temperature Grade	—	Industrial, -40°C to +100°C
Digital Termination	—	Digitally controlled termination supported