XA3S50-4PQG208Q vs XA3S50-4PQG208I 对比

详细并排对比 XA3S50-4PQG208Q 出自 AMD 和 XA3S50-4PQG208I 出自 Xilinx。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。

AMD

XA3S50-4PQG208Q - 125 MHz Spartan-3 XA FPGA | AMD

XA3S50-4PQG208Q Obsolete

Xilinx

XA3S50-4PQG208I ✓ 量产中

参数	XA3S50-4PQG208Q	XA3S50-4PQG208I
品牌	AMD	Xilinx
分类	FPGA & CPLD	FPGA & CPLD
生命周期状态	Obsolete	有效
Device Type	Field Programmable Gate Array (FPGA)	Spartan-3A automotive field-programmable gate array (FPGA)
FPGA Family	Spartan-3 XA	—
System Gates	50,000 gates	50,000 gates
Configurable Logic Blocks	192 CLBs	192 CLBs
Logic Cells	1,728 logic cells	1,728 logic elements
Maximum Operating Frequency	125 MHz	—
User I/O Pins	124 I/O	—
On-Chip RAM	73,728 bits	—
电源电压	1.2 V	—
Maximum Data Transfer Rate per I/O	622 Mb/s	—
Single-Ended I/O Standards	17 standards	17 standards
Differential I/O Standards	7 standards	7 standards, including LVDS
Differential I/O Support	LVDS	—
On-Chip Termination	Digitally Controlled	—
封装	208-pin PQFP	208-pin PQFP plastic quad flat package
Package Pin Pitch	0.50 mm	—
Terminal Form	Gull wing	—
Package Shape	Square	—
Automotive Qualification	AEC-Q100 qualified	AEC-Q100 automotive-grade designation reported in verified source data
工作温度范围	[DATA_NEEDED: operating temperature range]	—
Configuration Memory	[DATA_NEEDED: configuration memory type]	—
Static Power	[DATA_NEEDED: static power]	—
Dynamic Power	[DATA_NEEDED: dynamic power]	—
Total RAM Bits	—	73,728 bits
User I/O	—	124 I/O
Maximum Data Rate per I/O	—	622 Mb/s
Core Supply Voltage	—	1.2 V
I/O Supply Voltage	—	3.3 V
FPGA Technology	—	90 nm
Total Package Pins	—	208 pins
Speed Grade	—	-4
Temperature Grade	—	Industrial, -40°C to +100°C
Digital Termination	—	Digitally controlled termination supported