ADC12DS080CISQ/NOPB - Dual 12-Bit 80 MSPS ADC, Serial LVDS, 60-WQFN | Texas Instruments
Teilenummer: ADC12DS080CISQ/NOPB ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $32.5 | $32,50 |
| 10 | $28.95 | $289,50 |
| 100 | $24.5 | $2.450,00 |
| 500 | $21.2 | $10.600,00 |
| 1.000 | $18.75 | $18.750,00 |
| 3.000 | $16.8 | $50.400,00 |
ADC12DS080CISQ/NOPB Übersicht
An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts continuous-time analog voltages into discrete digital codes for processing by DSPs, FPGAs, or microcontrollers. The ADC12DS080 family sits inside the data-converter hierarchy as: ADC -> successive-approximation/pipelined ADC -> high-speed ADC -> mixed-signal IC. Dual-channel parts of this class are the workhorse building blocks of any system that digitizes I/Q baseband, two sensor channels, or differential analog signals simultaneously, enabling coherent multi-channel acquisition without per-channel skew.
The ADC12DS080CISQ/NOPB features a pipelined architecture with on-chip sample-and-hold, internal reference, and an LVDS serializer that delivers serialized data on a small number of differential pairs - simplifying PCB routing and reducing EMI compared to parallel CMOS outputs. It operates from a single 3.3 V analog supply and a 3.3 V digital supply, supports -40C to +85C industrial temperature range, and is offered in the Pb-free 60-WQFN package indicated by the /NOPB suffix.
The pipelined architecture delivers 12-bit linearity at high sample rates while the LVDS serializer eliminates wide parallel CMOS buses, reducing pin count, switching noise, and ground-bounce. Internal duty-cycle correction and programmable data-clock edge alignment let the host FPGA or ASIC capture data cleanly at full throughput without complex external calibration.
Typical applications include portable or bench-top oscilloscopes and digitizers, communications test equipment (cable modem downstream, Wi-Fi/4G baseband digitizers), medical imaging front ends such as ultrasound receivers, dual-sensor industrial data acquisition systems, and radar / LiDAR preprocessing where two channels must be sampled simultaneously.
When designing with this part, provide clean 3.3V analog and digital rails and decouple the AVDD/DVDD pins with separate ferrite-bead-isolated planes; route the LVDS pairs as 100 ohm differential and place the reference decoupling capacitor within 3 mm of the REF pins. Note that the /NOPB suffix confirms lead-free / RoHS compliance for global manufacturing.
This page synthesizes distributor pricing tiers, drop-in same-brand variants, and practical layout / decoupling notes not collected on the manufacturer product page.
Drop-in-Alternativen für ADC12DS080CISQ/NOPB – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Varianten dieser Serie
Modelle derselben Serie, die drop-in-kompatibel sind mit ADC12DS080CISQ/NOPB (gleiche Bauform und Footprint) – abweichend in Data Interface, Input Type, Operating Temperature, Resolution, Number of Channels.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
ADC12DS080CISQE/NOPB
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
ADC14DS080CISQ/NOPB
✅ Drop-In✓ Auf Lager
$20.85 / Stück
Datenblatt ansehen →ADC14DS105CISQE/NOPB
✅ Drop-In✓ Auf Lager
$24.95 / Stück
Datenblatt ansehen →ADC14C080CISQ/NOPB
✅ Drop-In✓ Auf Lager
$15.2 / Stück
Datenblatt ansehen →ADC12DC080CISQE/NOPB
✅ Drop-In✓ Auf Lager
$10.75 / Stück
Datenblatt ansehen →ADC12C105CISQ
✅ Drop-In✓ Auf Lager
$9.05 / Stück
Datenblatt ansehen →ADC12DS080CISQ/NOPB Grenzwerte & elektrische Eigenschaften
| Auflösung | 12 bits |
| Number of Channels | 2 (dual, simultaneous) |
| Sample Rate (per channel) | Up to 80 MSPS |
| Architecture | Pipelined |
| Input Type | Differential analog inputs |
| Data Interface | Serial LVDS (serialized outputs) |
| Digital Output Format | Serialized LVDS pairs (DDR / SDR selectable) |
| Analog Supply Voltage (AVDD) | 3.3 V (typical) |
| Digital Supply Voltage (DVDD) | 3.3 V (typical) |
| Betriebstemperaturbereich | -40C to +85C |
| Gehäuse / Bauform | 60-WFQFN Exposed Pad (WQFN-60, 9x9 mm) |
| Montageart | Surface Mount |
| Lead-Free / RoHS | Yes (Pb-free, /NOPB suffix) |
| Internal Reference | Yes (internal bandgap reference) |
ADC12DS080CISQ/NOPB Pin-Konfiguration
| Pin 1 | VA1M — Channel 1 negative analog input (differential) |
| Pin 2 | VA1P — Channel 1 positive analog input (differential) |
| Pin 3 | VBG — Internal bandgap reference (decouple to ground) |
| Pin 4 | VREF — Reference voltage (decouple to ground) |
| Pin 5 | AVDD — Analog 3.3V supply |
| Pin 6 | AGND — Analog ground |
| Pin 7 | CLK+ — Differential clock input (positive) |
| Pin 8 | CLK- — Differential clock input (negative) |
| Pin 9 | DCLKP — LVDS data clock output (positive) |
| Pin 10 | DCLKN — LVDS data clock output (negative) |
| Pin 11 | OP1+ — LVDS serialized data output, channel 1 (positive) |
| Pin 12 | OP1- — LVDS serialized data output, channel 1 (negative) |
| Pin 13 | OP0+ — LVDS serialized data output, channel 0 (positive) |
| Pin 14 | OP0- — LVDS serialized data output, channel 0 (negative) |
| Pin 15 | DVDD — Digital 3.3V supply |
| Pin 16 | DGND — Digital ground |
| Pin 17-30 | NC — Not connected (per datasheet package diagram) |
| Pin 31-58 | NC — Not connected (per datasheet package diagram) |
| Pin 59 | VA0M — Channel 0 negative analog input (differential) |
| Pin 60 | VA0P — Channel 0 positive analog input (differential) |
Typische Anwendungen
ADC12DS080CISQ/NOPB ist geeignet für 6 Anwendungs: Portable Oscilloscope / Digitizer Front End, Communications Test Equipment / Cable Modem Downstream, Medical Imaging / Ultrasound Receiver, Industrial Dual-Sensor Data Acquisition, Radar / LiDAR Preprocessing, Software Defined Radio / Wideband Receiver.
Portable Oscilloscope / Digitizer Front End
The ADC12DS080CISQ/NOPB is well suited to portable two-channel oscilloscope and digitizer front ends where two input channels must be captured simultaneously at up to 80 MSPS each. Its serialized LVDS outputs pair cleanly with cost-effective FPGAs (e.g., Xilinx Spartan-6/7 or Lattice ECP5) over a small number of differential pairs, keeping PCB routing density low while preserving 12-bit vertical resolution. The 60-WQFN package's exposed pad handles typical 700 mW - 1 W dissipation without a heatsink, ideal for handheld form factors. Designers typically feed the two analog channels from front-end amplifiers (TI THS4631 or Analog Devices AD8138) and capture data into on-chip FPGA memory for real-time display or USB streaming.
Empfohlen
Communications Test Equipment / Cable Modem Downstream
In communications test equipment and cable-modem downstream digitizers, the ADC12DS080CISQ/NOPB's dual 80 MSPS channels digitize I/Q baseband or dual downstream carriers simultaneously without skew. The serialized LVDS interface avoids the wide parallel CMOS bus that would otherwise inject switching noise into the sensitive analog front end - critical at the 100 MHz+ IF frequencies typical in DOCSIS 3.x line cards. The 3.3 V analog/digital supplies simplify power-tree design, while the -40C to +85C industrial temperature grade suits outdoor line-card enclosures. The LVDS lanes fan into a small FPGA or ASIC that performs FFT-based downstream demodulation.
Empfohlen
Medical Imaging / Ultrasound Receiver
Ultrasound receiver boards digitize multiple channel pairs at once, and the ADC12DS080CISQ/NOPB's dual simultaneous 80 MSPS channels allow designers to time-share two channels per IC across an array of receive channels, halving board area versus single-channel 12-bit ADCs. The pipelined architecture delivers 12-bit linearity with low latency - important for beam-forming loops. The 60-WQFN package exposes the thermal pad for ground-plane cooling at sustained 80 MSPS operation. The serialized LVDS interface connects to FPGAs that perform Hilbert-transform demodulation and envelope detection across many channels in parallel.
Empfohlen
Industrial Dual-Sensor Data Acquisition
In factory-floor and process-control data acquisition, the ADC12DS080CISQ/NOPB simultaneously digitizes two sensor channels (strain gauge bridge pairs, dual-axis transducers, or vibration sensor pairs) without time-skew. The 80 MSPS per-channel bandwidth comfortably oversamples 50-100 kHz industrial transducers, allowing digital filtering to push effective ENOB beyond 12 bits. The -40C to +85C industrial temperature range covers outdoor cabinets and factory environments. The serialized LVDS outputs travel cleanly to an FPGA or industrial MCU over shielded twisted pairs, eliminating the wide CMOS bus that would otherwise couple noise into adjacent analog rails.
Empfohlen
Radar / LiDAR Preprocessing
Automotive and industrial radar/LiDAR preprocessing boards digitize two channels of IF or photodiode signals at high speed, and the ADC12DS080CISQ/NOPB's dual 80 MSPS input channels serve as a compact, low-cost front end. The serialized LVDS interface minimizes routing in the dense antenna-array PCB environment. The 60-WQFN exposed pad maintains acceptable junction temperature even at sustained 80 MSPS dual-channel operation. An FPGA downstream performs FFT-based range/Doppler processing; multiple ADC12DS080CISQ/NOPB parts can be tiled across an array with synchronized clocks for coherent multi-channel acquisition.
Empfohlen
Software Defined Radio / Wideband Receiver
Software-defined radio (SDR) wideband receivers digitize I/Q baseband directly at IF or near-RF, and the ADC12DS080CISQ/NOPB's two simultaneous 80 MSPS channels capture the I and Q streams with matched gain and phase - essential for downstream digital down-conversion. The serialized LVDS outputs feed into an FPGA that performs digital mixing, decimation, and channelization. The 60-WQFN package's small footprint allows compact SDR modules for portable or airborne platforms. Designers typically pair the part with TI LMX2582 or Analog Devices ADF4351 wideband synthesizers for the local oscillator.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für ADC12DS080CISQ/NOPB – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | ADC12DS080CISQE/NOPB | ADC14DS080CISQ/NOPB | ADC12DC080CISQE/NOPB | ADC12C105CISQ | ADC14DS105CISQE/NOPB |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 60-WQFN (9x9) | 60-WQFN (9x9) - same | 60-WQFN (9x9) - same family | 60-WQFN (9x9) - same | 60-WQFN (9x9) - same | 60-WQFN (9x9) - same family |
| Resolution | 12 bits | 12 bits | 14 bits | 12 bits | 12 bits | 14 bits |
| Sample Rate (per channel) | 80 MSPS | 80 MSPS | 80 MSPS | 80 MSPS | 105 MSPS | 105 MSPS |
| Number of Channels | 2 | 2 | 2 | 2 | 2 | 2 |
| Digital Output | Serialized LVDS | Serialized LVDS | Serialized LVDS | LVDS DDR (parallel) | Serialized LVDS | Serialized LVDS |
| Supply Voltage | 3.3V AVDD / 3.3V DVDD | 3.3V / 3.3V | 3.3V / 3.3V | 3.3V / 3.3V | 3.3V / 3.3V | 3.3V / 3.3V |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
Wichtigste Unterscheidungsmerkmale
- Serialized LVDS output reduces external pin count and PCB routing complexity (vs. ADC12DC080CISQE/NOPB)
- Higher resolution upgrade path on the same 60-WQFN footprint (vs. ADC14DS080CISQ/NOPB)
- Higher sample rate upgrade path on the same 60-WQFN footprint (vs. ADC12C105CISQ)
Designhinweise
Provide a clean 3.3V analog supply (AVDD) and a separate 3.3V digital supply (DVDD) joined at a single ferrite bead near the IC. Each AVDD/DVDD pin pair must have its own 0.1 uF X7R ceramic bypass capacitor placed within 3 mm of the pin, plus a 10 uF tantalum or polymer bulk capacitor to handle LVDS output switching transients. Avoid routing digital return currents through the analog ground plane.
The 60-WQFN exposed thermal pad must be soldered to a continuous ground plane with at least 9 thermal vias (12 mil drill, 25 mil pitch) for heat dissipation. Place the analog input traces as a 100 ohm differential pair using controlled impedance, and keep them short and away from the LVDS output pairs to minimize coupling. Use separate analog and digital ground regions joined under the IC.
Do not leave the reference pin (VREF) floating - it requires a 10 uF X7R decoupling capacitor returned to analog ground within 3 mm. Do not route the LVDS pairs without 100 ohm differential impedance; mismatched impedance causes inter-pair skew and degraded SNR. When using the serialized LVDS mode, ensure the FPGA deserializer is configured for the correct lane mapping (OP0+/OP0- for channel 0, OP1+/OP1- for channel 1) or channels will be swapped.
Estimated: at full 80 MSPS per-channel dual operation, the IC's aggregate LVDS output toggling rate is approximately 960 Mbps per LVDS pair, producing edge rates of ~250 ps. Maintain a continuous reference plane under the LVDS pairs and avoid via transitions within the pair. Use length-matching within 5 mil between P and N to keep common-mode rejection high; place an LVDS 100 ohm termination resistor at the FPGA receiver end only.
Compliance-Informationen
Pb-free / RoHS compliance confirmed by the /NOPB suffix in the TI ordering code and the product page on ti.com. AEC-Q100 automotive qualification is not applicable (industrial-temperature grade only).
