ATSAMA5D28C-LD2G-CU - 500MHz Cortex-A5 MPU, 2Gbit LPDDR2 SiP | Microchip
Teilenummer: ATSAMA5D28C-LD2G-CU ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $20.58 | $20,58 |
| 10 | $19.45 | $194,50 |
| 100 | $18.2 | $1.820,00 |
| 500 | $16.95 | $8.475,00 |
| 1.000 | $15.75 | $15.750,00 |
ATSAMA5D28C-LD2G-CU Übersicht
What is a System-in-Package (SiP) MPU? An SiP integrates a processor die and one or more memory/companion dies inside a single BGA package, allowing engineers to treat the assembly as a single component on the PCB. Compared to a discrete MPU + external DDR2/LPDDR2 design, an SiP shortens critical trace lengths, reduces EMI susceptibility, and simplifies PCB routing. The SAMA5D2 family belongs to the Cortex-A5 class of 32-bit application processors — sitting in the taxonomy: Cortex-A5 -> Arm application processor -> MPU -> embedded microprocessor -> integrated circuit — and is widely used in human-machine interface (HMI), industrial control, and connected IoT edge nodes.
Key features of the ATSAMA5D28C-LD2G-CU include: an Arm Cortex-A5 core with Arm NEON and FPU, hardware cryptographic acceleration (AES, SHA, TRNG), a 32-bit LPDDR2/DDR2/LPDDR3/DDR3 memory controller, dual Ethernet GMAC, dual CAN-FD, multiple USB 2.0 High-Speed ports (host and device), up to three SD/SDIO/MMC interfaces, an LCD controller supporting up to WXGA, a 12-bit ADC, and a 12-bit DAC. The integrated 2 Gbit LPDDR2 provides ample headroom for Linux- and RTOS-based GUI stacks, while secure-boot and tamper-detection pins support anti-cloning and DRM use cases.
Architecturally, the device pairs a high-throughput Cortex-A5 pipeline with a low-power island for always-on peripherals, enabling fast wake/sleep transitions. Industrial-grade peripherals include Class-D audio interfaces and image-sensor parallel ports, while the on-chip crypto block removes the need for an external secure-element in many designs.
Typical applications include industrial HMI panels, smart-home gateways, point-of-sale terminals, building-automation controllers, and connected IoT edge nodes. Designers should follow Microchip's SAMA5D2 hardware guidelines for power-rail sequencing and PCB stack-up — the SiP's internal memory routing constrains the board layer count and demands 4 or more layers with controlled-impedance routing for USB and Ethernet. This page consolidates distributor pricing, drop-in alternatives within the SAMA5D2 family, and engineering design notes that go beyond what is found in the manufacturer datasheet alone.
Drop-in-Alternativen für ATSAMA5D28C-LD2G-CU – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Varianten dieser Serie
Modelle derselben Serie, die drop-in-kompatibel sind mit ATSAMA5D28C-LD2G-CU (gleiche Bauform und Footprint) – abweichend in Package, Operating Temperature, Ethernet, USB, Core Architecture.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
ATSAMA5D28C-LD1G-CUR
✅ Drop-In✓ Auf Lager
$19.4 / Stück
Datenblatt ansehen →ATSAMA5D28C-D1G-CU
✅ Drop-In✓ Auf Lager
$23.5 / Stück
Datenblatt ansehen →ATSAMA5D28B-CUR
✅ Drop-In✓ Auf Lager
$12.6 / Stück
Datenblatt ansehen →ATSAMA5D28B-CNR
✅ Drop-In✓ Auf Lager
$17.9 / Stück
Datenblatt ansehen →ATSAMA5D27C-D1G-CU
✅ Drop-In✓ Auf Lager
$19.1 / Stück
Datenblatt ansehen →ATSAMA5D26C-CU
✅ Drop-In✓ Auf Lager
$11.8 / Stück
Datenblatt ansehen →ATSAMA5D28C-LD2G-CU Grenzwerte & elektrische Eigenschaften
| Core Architecture | Arm Cortex-A5 (32-bit) with NEON and FPU |
| Maximum CPU Clock | 500 MHz |
| Core Count | 1 |
| Integrated Memory (SiP) | 2 Gbit LPDDR2 SDRAM |
| External Memory Support | DDR2/DDR3L/LPDDR2/LPDDR3, QSPI, e.MMC Flash |
| Gehäuse | 289-ball LFBGA (14x14 mm) |
| Betriebstemperatur | -40C to +85C (Industrial) |
| Graphics / Display | LCD controller up to WXGA resolution |
| Ethernet | 2x 10/100/1000 GMAC |
| USB | 2x USB 2.0 High-Speed (Host + Device) |
| CAN | 2x CAN-FD |
| SD/MMC | Up to 3x SD/SDIO/MMC |
| ADC / DAC | 12-bit ADC, 12-bit DAC |
| Cryptography | AES, SHA, TRNG, secure boot |
| RoHS-Status | Compliant |
| Montageart | Surface Mount (BGA) |
ATSAMA5D28C-LD2G-CU 289-ball lfbga (14x14 mm) Pinbelegungsleitfaden
Pinbelegung für ATSAMA5D28C-LD2G-CU (289-ball lfbga (14x14 mm)-Gehäuse). Dieser digitale IC umfasst GPIO, Kommunikationsschnittstellen (UART, SPI, I2C) und Versorgungspins. Alternative Pin-Funktionen und Konfigurationsoptionen entnehmen Sie dem Herstellerdatenblatt. Unverzichtbar für Embedded-System-Design und PCB-Layout.
Keine detaillierten Pinbelegungsdaten verfügbar für ATSAMA5D28C-LD2G-CU.
Siehe die Datenblatt für die vollständige Pin-Konfiguration.
Typische Anwendungen
ATSAMA5D28C-LD2G-CU ist geeignet für 6 Anwendungs: Industrial HMI Panels, Smart Home / IoT Edge Gateways, Point-of-Sale Terminals, Building Automation Controllers, Connected Medical Devices, Audio/Class-D Amplifier Hosts.
Industrial HMI Panels
The ATSAMA5D28C-LD2G-CU's 500 MHz Cortex-A5 core, integrated LCD controller supporting up to WXGA resolution, and 2 Gbit of LPDDR2 (256 MB) provide ample throughput and framebuffer headroom for graphical human-machine interfaces in factory automation and process-control panels. Hardware crypto and secure-boot enable signed firmware rollouts on the factory floor. The industrial temperature range (-40C to +85C) and dual CAN-FD support deterministic fieldbus connectivity alongside the touchscreen stack.
Empfohlen
Smart Home / IoT Edge Gateways
Dual Gigabit Ethernet GMAC, dual CAN-FD, and dual USB 2.0 High-Speed ports let the ATSAMA5D28C-LD2G-CU aggregate multiple radios and fieldbuses in a residential or commercial gateway. The integrated 2 Gbit LPDDR2 supports TLS handshake memory pools, MQTT brokers, and on-device edge analytics without external DRAM. Hardware AES/SHA offload accelerates encrypted traffic at line rate, and the LPDDR2 self-refresh modes cut standby power for always-listening IoT designs.
Empfohlen
Point-of-Sale Terminals
POS terminals need a secure, responsive UI plus encrypted card-data handling — exactly the workload the ATSAMA5D28C-LD2G-CU is built for. The hardware AES/SHA/TRNG block accelerates PCI-compliant card-data encryption without burdening the Cortex-A5 core, while the integrated 256 MB LPDDR2 holds the OS, UI, and transaction buffers. The LCD controller drives the operator and customer displays, and dual Ethernet supports segregated payment-vs-management networks.
Empfohlen
Building Automation Controllers
Building controllers integrate HVAC, lighting, access, and metering — the ATSAMA5D28C-LD2G-CU's dual CAN-FD bus, Ethernet, USB, and 12-bit ADC cover all of these on one chip. Industrial temperature grading ensures 24/7 operation in mechanical rooms. The 2 Gbit LPDDR2 runs a full Linux stack with BACnet/Modbus gateways, while secure-boot and tamper pins protect against physical and firmware tampering on-site.
Empfohlen
Connected Medical Devices
Patient monitors and diagnostic peripherals benefit from the ATSAMA5D28C-LD2G-CU's secure-boot chain, hardware cryptography for HIPAA-compliant data-at-rest, and rich display capability for clinician-facing screens. The 500 MHz Cortex-A5 runs embedded Linux or a real-time OS with deterministic peripheral response, and the 12-bit ADC supports direct connection to sensor front-ends. Industrial temperature range plus LPDDR2's low active power suit battery-backed portable carts.
Empfohlen
Audio/Class-D Amplifier Hosts
The ATSAMA5D28C-LD2G-CU integrates Class-D amplifier interfaces alongside I2S/TDM, enabling multi-zone audio amplifiers with on-device stream decryption and per-zone EQ. The 2 Gbit LPDDR2 buffers uncompressed audio streams for whole-house audio systems, and the Cortex-A5 + NEON DSP extensions accelerate software codecs (Opus, LC3, AAC). Hardware AES offload unlocks premium content delivery without burdening the application core.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für ATSAMA5D28C-LD2G-CU – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | ATSAMA5D28C-LD1G-CUR | ATSAMA5D28C-D1G-CU | ATSAMA5D28B-CU | ATSAMA5D27C-D1G-CU | ATSAMA5D26C-CU |
|---|---|---|---|---|---|---|
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Package | 289-LFBGA (14x14 mm) | 289-LFBGA (14x14 mm) - same | 289-LFBGA (14x14 mm) - same | 289-LFBGA (14x14 mm) - same | 289-LFBGA (14x14 mm) - same | 289-LFBGA (14x14 mm) - same |
| Integrated Memory | 2 Gbit LPDDR2 | 1 Gbit LPDDR2 | 1 Gbit DDR2 | 2 Gbit LPDDR2 (B silicon) | 1 Gbit DDR2 | External DDR2 (no SiP) |
| CPU Core | Cortex-A5 500 MHz | Cortex-A5 500 MHz | Cortex-A5 500 MHz | Cortex-A5 500 MHz | Cortex-A5 500 MHz | Cortex-A5 500 MHz |
| Silicon Revision | C | C | C | B | C | C |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) |
| RoHS Compliance | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant |
Wichtigste Unterscheidungsmerkmale
- Highest integrated memory density in the SAMA5D2 family (vs. ATSAMA5D28C-LD1G-CUR)
- LPDDR2 power efficiency vs DDR2 alternatives (vs. ATSAMA5D28C-D1G-CU)
- Latest silicon revision with bug fixes and security hardening (vs. ATSAMA5D28B-CU)
Designhinweise
Estimated: The 289-ball LFBGA (14x14 mm, ~0.5-0.8 mm pitch) demands a 4-layer minimum PCB stack-up with continuous GND planes under the SiP and matched-length impedance-controlled traces for USB 2.0 High-Speed (90 ohm differential) and Gigabit Ethernet (100 ohm differential). Place the SiP away from switching DC-DC nodes; the integrated LPDDR2 is sensitive to switching-noise coupling through VDDLDO. Follow Microchip's SAMA5D2 hardware design checklist for ball-A1 orientation and decouple VDDANA/VDDPLL/VDDUTMIC pairs with 100 nF X7R plus 10 uF bulk per the reference schematic.
Estimated: At maximum CPU load (500 MHz, peripherals active) the SiP dissipates roughly 1-1.5 W. With a properly stitched GND plane beneath the LFBGA, junction-to-ambient theta_JA is typically 25-35 C/W on a 4-layer JEDEC board, giving a 25-50 C temperature rise. For sealed industrial enclosures without forced airflow, derate CPU frequency to 400 MHz or add a thermal pad connecting the BGA's central GND balls to an inner copper pour to keep Tj below 105 C at 85 C ambient.
Do not confuse the LD2G (LPDDR2, 2 Gbit) suffix with D2G (DDR2, 2 Gbit) — they have different internal DRAM dies and different power-rail requirements (LPDDR2 needs 1.2 V VDDLPDDR with self-refresh, DDR2 needs 1.8 V). Mixing the two will cause boot failures or DRAM initialization hangs. Also note the trailing -CU vs -CUR: -CU ships in tray-pack, -CUR ships in tape-and-reel — same die and pinout, only packaging differs.
Sequence the SAMA5D2 power rails per Microchip's 'Power Management' section: VDDLDO_IN first, then VDDLDO_OUT (1.2 V), then VDDANA/VDDPLL/VDDUTMIC, then VDDLPDDR (for LD variants). Holding the NRST line low until all rails are stable prevents latch-up. The LPDDR2 self-refresh current is approximately 200-400 uA at 25 C — design the backup-supply path for at least 1 mA to cover worst-case temperature drift.
Compliance-Informationen
RoHS and REACH compliance per Microchip product page. Industrial temperature grade -40C to +85C. Not AEC-Q100 qualified (consumer/industrial MPU); not designed for automotive safety-critical applications.
