KSZ9031RNXCC - Gigabit Ethernet PHY RGMII | Microchip
Teilenummer: KSZ9031RNXCC ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $6.42 | $6,42 |
| 10 | $5.78 | $57,80 |
| 100 | $5.1 | $510,00 |
| 500 | $4.55 | $2.275,00 |
| 1.000 | $4.05 | $4.050,00 |
KSZ9031RNXCC Übersicht
A Gigabit Ethernet PHY (physical-layer transceiver) is the analog front-end of a wired Ethernet link, translating between digital MAC data and differential signaling on the copper cable while performing auto-negotiation, link training, and signal integrity compensation. Within the network hierarchy, the PHY sits below the MAC (media access controller) and above the magnetics + RJ-45 connector; together they form the OSI Layer-1 / Layer-2 boundary of an Ethernet port. KSZ9031RNXCC is part of Microchip's KSZ9031 family of integrated triple-speed PHYs and targets Gigabit Ethernet designs requiring low BOM cost.
Key features include on-chip termination resistors for the four differential pairs, integrated LDO controller to drive a low-cost external MOSFET for the 1.2V core supply, automatic correction of differential pair misplacements and polarity reversals, programmable propagation delay compensation, and LinkMD cable diagnostics. The device also supports Energy Efficient Ethernet (EEE) IEEE 802.3az, Wake-on-LAN, and a hardware power-down (CPD) mode that draws only a few milliamps.
The KSZ9031RNXCC uses a 1.2V core derived from an internal regulator that requires only a single external MOSFET and bypass caps, reducing total BOM by eliminating a standalone 1.2V LDO. The RGMII Version 2.0 timing is provided on-chip, so most designs need no external delay lines on the MAC-to-PHY strobe traces, which simplifies PCB layout. AEC-Q100 automotive qualification is available on certain KSZ9031 variants (consult the KSZ9031 family datasheet for specific ordering codes), making the device attractive for in-vehicle networking as well as industrial Ethernet.
Typical applications include Gigabit Ethernet switches and routers, industrial control and factory automation nodes, set-top boxes and IPTV gateways, network-attached storage (NAS), automotive infotainment backbones, and any embedded Linux or RTOS board that needs a CAT-5 wired uplink with low component count.
When designing with this part, follow the Microchip reference schematic: route the four MDI differential pairs with 100-ohm differential impedance and length matching within 50 mils, place the 1.2V MOSFET and bulk capacitors as close to the chip as possible, and use strap resistors on MODE[3:0] to set the default PHY address and operating mode. After hardware reset, software can re-program all strap options via the MDIO/MDC management interface.
This page consolidates distributor pricing, drop-in alternatives within the same 48-QFN footprint, and practical design notes not found in the manufacturer datasheet alone, giving engineers a single reference for board bring-up and second-sourcing decisions.
Drop-in-Alternativen für KSZ9031RNXCC – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Varianten dieser Serie
Modelle derselben Serie, die drop-in-kompatibel sind mit KSZ9031RNXCC (gleiche Bauform und Footprint) – abweichend in Package, MAC Interface, Data Rate, Operating Temperature, Cable Type.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
KSZ9131RNX
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
KSZ9031RNXVA
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
KSZ9031RNXIC
✅ Drop-In✓ Auf Lager
$4.35 / Stück
Datenblatt ansehen →KSZ9031RNXCA
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
DP83867IRRGZ
✅ Drop-In✓ Auf Lager
$6.88 / Stück
Datenblatt ansehen →KSZ9031RNXCC Technische Daten
| Product Type | Ethernet Physical Layer Transceiver (PHY) |
| Datenrate | 10 / 100 / 1000 Mbps (triple-speed) |
| Standards | IEEE 802.3, 802.3u, 802.3ab, 802.3az (EEE) |
| MAC Interface | RGMII (Version 2.0 compliant, on-chip delay) |
| Cable Interface | 4 differential pairs, CAT-5 UTP, 100-ohm differential |
| Management Interface | MDIO / MDC (IEEE 802.3 clause 22/45) |
| Supply Voltage (Analog/DVDD) | 3.3 V |
| Core Supply | 1.2 V (on-chip LDO controller + external MOSFET) |
| On-chip Features | Termination resistors, LinkMD cable diagnostics, auto-negotiation, polarity correction |
| Power Saving | Energy Efficient Ethernet (EEE) IEEE 802.3az, Wake-on-LAN, hardware CPD mode |
| Gehäuse | 48-pin QFN (7x7 mm) |
| Montageart | Surface Mount |
| Betriebstemperatur | 0C to +70C (commercial grade, CC suffix) |
| MSL-Level | 3 |
| RoHS-Status | Compliant |
KSZ9031RNXCC Pin-Konfiguration
| Pin 1 | VDD_1V2 — 1.2V core supply output (LDO controller drives external MOSFET) |
| Pin 2 | VDDA — 3.3V analog supply |
| Pin 3 | TX_CLK — RGMII transmit clock |
| Pin 4 | TX_D0 — RGMII transmit data bit 0 |
| Pin 5 | TX_D1 — RGMII transmit data bit 1 |
| Pin 6 | TX_D2 — RGMII transmit data bit 2 |
| Pin 7 | TX_D3 — RGMII transmit data bit 3 |
| Pin 8 | TX_CTL — RGMII transmit control (TX_EN / TX_ER multiplexed) |
| Pin 9 | GND — Ground |
| Pin 10 | RX_CLK — RGMII receive clock |
| Pin 11 | RX_D0 — RGMII receive data bit 0 |
| Pin 12 | RX_D1 — RGMII receive data bit 1 |
| Pin 13 | RX_D2 — RGMII receive data bit 2 |
| Pin 14 | RX_D3 — RGMII receive data bit 3 |
| Pin 15 | RX_CTL — RGMII receive control (RX_DV / RX_ER multiplexed) |
| Pin 16 | MDC — Management data clock |
| Pin 17 | MDIO — Management data I/O |
| Pin 18 | INT_N — Interrupt output (active low) |
| Pin 19 | RESET_N — Hardware reset (active low) |
| Pin 20 | CLK_OUT — Reference clock output |
| Pin 21 | MODE0 — Strap-in mode select bit 0 |
| Pin 22 | MODE1 — Strap-in mode select bit 1 |
| Pin 23 | MODE2 — Strap-in mode select bit 2 |
| Pin 24 | MODE3 — Strap-in mode select bit 3 |
| Pin 25 | LED0 — Activity/link LED output 0 |
| Pin 26 | LED1 — Activity/link LED output 1 |
| Pin 27 | LED2 — Activity/link LED output 2 |
| Pin 28 | NC — Not connected (per datasheet) |
| Pin 29 | GND — Ground |
| Pin 30 | MDI_A_P — MDI pair A positive (1000Base-T lane 0) |
| Pin 31 | MDI_A_N — MDI pair A negative (1000Base-T lane 0) |
| Pin 32 | MDI_B_P — MDI pair B positive (1000Base-T lane 1) |
| Pin 33 | MDI_B_N — MDI pair B negative (1000Base-T lane 1) |
| Pin 34 | GND — Ground |
| Pin 35 | MDI_C_P — MDI pair C positive (1000Base-T lane 2) |
| Pin 36 | MDI_C_N — MDI pair C negative (1000Base-T lane 2) |
| Pin 37 | MDI_D_P — MDI pair D positive (1000Base-T lane 3) |
| Pin 38 | MDI_D_N — MDI pair D negative (1000Base-T lane 3) |
| Pin 39 | GND — Ground |
| Pin 40 | NC — Not connected (per datasheet) |
| Pin 41 | VDDA — 3.3V analog supply |
| Pin 42 | VDDIO — 3.3V I/O supply |
| Pin 43 | NC — Not connected (per datasheet) |
| Pin 44 | NC — Not connected (per datasheet) |
| Pin 45 | NC — Not connected (per datasheet) |
| Pin 46 | NC — Not connected (per datasheet) |
| Pin 47 | NC — Not connected (per datasheet) |
| Pin 48 | VDD_1V2 — 1.2V core supply (LDO output) |
Typische Anwendungen
KSZ9031RNXCC ist geeignet für 6 Anwendungs: Gigabit Ethernet Switches and Routers, Industrial Ethernet and Factory Automation, Network Attached Storage (NAS) and Servers, Set-Top Boxes, IPTV, and Media Gateways, Automotive Infotainment and ADAS Networking, Embedded Linux / RTOS Single-Board Computers.
Gigabit Ethernet Switches and Routers
The KSZ9031RNXCC is well suited to Gigabit Ethernet switch and router ports because it provides a fully integrated 10/100/1000Base-T PHY with RGMII to the switch ASIC or SoC MAC. Its on-chip 100-ohm termination on the four MDI pairs removes the need for external termination resistor networks, and the integrated LDO controller driving a low-cost external MOSFET eliminates a separate 1.2V regulator. Per the datasheet, on-chip RGMII Version 2.0 delay timing removes the requirement for external clock-delay traces, simplifying board layout and reducing BOM cost. This makes it a natural choice for cost-sensitive 8-port to 48-port unmanaged or lightly managed switches where each port's BOM must be minimized.
Empfohlen
Industrial Ethernet and Factory Automation
In factory automation nodes, PLCs, and industrial Ethernet gateways, the KSZ9031RNXCC provides a robust 1000Base-T uplink that is compatible with standard CAT-5 cabling commonly used on the plant floor. The LinkMD cable diagnostics feature (per the KSZ9031RNX datasheet) lets the host diagnose cable opens, shorts, and length, which is critical for predictive maintenance in industrial environments. Combined with the commercial 0C to +70C operating range and proven CAT-5 interoperability, it is widely used in industrial PCs, HMIs, and motor-drive controllers that need a deterministic wired uplink back to the control network.
Empfohlen
Network Attached Storage (NAS) and Servers
NAS enclosures, small-form-factor servers, and home-server boards benefit from the KSZ9031RNXCC's Gigabit throughput, RGMII interface to common SoCs, and small 48-QFN footprint that fits tight board layouts around CPU sockets. The 1000Base-T link saturates a SATA SSD array and provides wire-speed transfers to the LAN. The on-chip cable diagnostics also help end users troubleshoot cabling issues, and the hardware CPD (chip power-down) mode plus IEEE 802.3az EEE reduce idle power consumption in always-on storage appliances where every watt of idle power matters over a year of operation.
Empfohlen
Set-Top Boxes, IPTV, and Media Gateways
Set-top boxes, IPTV gateways, and Over-the-Top (OTT) media adapters require a single Gigabit Ethernet port to deliver high-bitrate video streams. The KSZ9031RNXCC's RGMII interface connects directly to the SoC's Ethernet MAC, and its triple-speed auto-negotiation ensures compatibility with older 10/100 switches on legacy home networks. Energy Efficient Ethernet (IEEE 802.3az) support reduces power draw when streaming is paused or during standby, helping meet stringent energy-consumption regulations like the EU Lot 26 network-standby requirements. The compact 48-QFN (7x7) footprint also fits inside slim-line STB enclosures where PCB real estate is at a premium.
Empfohlen
Automotive Infotainment and ADAS Networking
For in-vehicle networking, the KSZ9031 family (in AEC-Q100-qualified variants) provides a 1000Base-T automotive Ethernet PHY that supports high-bandwidth backbone links between infotainment head units, ADAS domain controllers, and rear-seat entertainment modules. The 48-QFN package, RGMII host interface, and integrated termination suit space-constrained automotive PCBs, while on-chip polarity correction and propagation-delay compensation simplify harness and connector tolerance. Note that the specific AEC-Q100 ordering codes are different from the KSZ9031RNXCC commercial part, so designers should select the appropriate automotive-grade variant from the KSZ9031 family for production vehicles.
Empfohlen
Embedded Linux / RTOS Single-Board Computers
Single-board computers, IoT gateways, and developer boards running Linux or an RTOS typically need a wired Gigabit Ethernet port for development, network boot, and reliable connectivity. The KSZ9031RNXCC's RGMII interface is supported natively by the Ethernet MACs in NXP i.MX, TI Sitara, Microchip SAMA5, and Broadcom SoCs, with mainline Linux drivers in the kernel PHY subsystem. The Microchip reference schematic and evaluation board documentation shorten bring-up time, and the integrated LDO controller minimizes external components on cost-sensitive hobbyist and prosumer boards such as those in the open-source hardware community.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für KSZ9031RNXCC – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | KSZ9131RNX | KSZ9031RNXVA | KSZ9031RNXIC | DP83867IRRGZ |
|---|---|---|---|---|---|
| Package | 48-QFN (7x7) | 48-QFN (7x7) - same | 48-QFN (7x7) - same | 48-QFN (7x7) - same | 48-QFN (7x7) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Texas Instruments |
| Data Rate | 10/100/1000 Mbps | 10/100/1000 Mbps + 100Base-T1/1000Base-T1 | 10/100/1000 Mbps | 10/100/1000 Mbps | 10/100/1000 Mbps |
| MAC Interface | RGMII v2.0 | RGMII v2.0 | RGMII v2.0 | RGMII v2.0 | RGMII v2.0 |
| Core Supply | 1.2V internal LDO + ext MOSFET | 1.2V internal LDO + ext MOSFET | 1.2V internal LDO + ext MOSFET | 1.2V internal LDO + ext MOSFET | 1.0V / 2.5V external rails required |
| EEE (802.3az) | Yes | Yes | Yes | Yes | Yes |
| Operating Temperature | 0C to +70C (CC) | 0C to +70C (commercial) | -40C to +85C (industrial VA grade) | -40C to +85C (industrial grade) | -40C to +85C (industrial) |
| Cable Diagnostics | LinkMD | LinkMD (improved) | LinkMD | LinkMD | Integrated cable diagnostic |
Wichtigste Unterscheidungsmerkmale
- Integrated LDO controller reduces BOM vs TI cross-brand PHYs (vs. DP83867IRRGZ)
- On-chip RGMII v2.0 delay timing removes external delay lines (vs. KSZ9031RNXVA)
- Upgrade path to KSZ9131RNX is fully pin-compatible (vs. KSZ9131RNX)
Designhinweise
Route the four MDI differential pairs (MDI_A through MDI_D) with 100-ohm differential impedance and length-match each pair to within 50 mils (about 1.25 mm). Keep the MDI traces away from switching power nodes and clock edges, and place the 1.2V decoupling caps and the LDO-controller MOSFET within 3-5 mm of pins 1/48. The exposed thermal pad must be soldered to a continuous ground plane with at least 9 thermal vias to a lower ground layer for proper heat dissipation, as recommended in the KSZ9031RNX datasheet layout section.
Power sequencing: 3.3V (VDDA / VDDIO) must be stable before the 1.2V core rail is allowed to rise, otherwise internal ESD cells may be stressed. With the integrated LDO controller, this is automatic as long as the external MOSFET gate is referenced to 3.3V, but verify the rise time of 3.3V is less than 50 ms in your power-tree design. Add a 22 uF bulk + 0.1 uF + 1 nF decoupling network on each 3.3V pin, and a 10 uF + 0.1 uF network on the 1.2V rail right at the chip.
Common pitfalls: (1) Forgetting to strap MODE[3:0] - leaving them floating causes undefined PHY address and operating mode; use 4.7 kohm pull-ups or pull-downs to set defaults. (2) Skipping MDIO pull-up - MDIO is an open-drain bus and requires a 1.5 kohm pull-up to 3.3V; without it, register access fails. (3) Using too-large magnetics - the KSZ9031RNX datasheet specifies 1:1 turns ratio with center-tap and 350 uH OCL minimum; using smaller magnetics can cause 1000Base-T link failures. (4) Failing to enable the CLK_OUT reference clock output if the SoC MAC needs a 25 MHz reference, otherwise RGMII timing will be unstable.
Compliance-Informationen
Per Microchip product page and PartGenie compliance data: RoHS compliant, lead-free QFN package. KSZ9031RNXCC itself is not AEC-Q100 qualified - the automotive-grade equivalents are different ordering codes in the KSZ9031 family.
