LTC2122CUK - Dual 14-bit 170Msps ADC with JESD204B | ADI
Teilenummer: LTC2122CUK ✓ Aktiv| Menge | Stückpreis | Gesamt |
|---|---|---|
| 1 | $95 | $95,00 |
| 10 | $90.25 | $902,50 |
| 100 | $88.13 | $8.813,00 |
| 500 | $85.5 | $42.750,00 |
| 1.000 | $83 | $83.000,00 |
LTC2122CUK Übersicht
What is a JESD204B ADC? JESD204B is a high-speed serial interface standard (JEDEC JESD204B, revision 2011) that converts parallel ADC data into serialized lanes running at multi-gigabit rates. It reduces PCB routing congestion by replacing wide parallel LVDS buses with 1-8 differential lanes, simplifying layout for multi-Gsps converters used in communications, radar, and test instrumentation. As a pipelined dual-channel converter with serial outputs, the LTC2122CUK sits in the hierarchy: ADC -> data converter -> signal chain IC -> semiconductor.
Key features include a 1.25GHz analog input bandwidth that enables reliable IF under-sampling, integrated input buffers to ease front-end matching, and sub-clock jitter performance optimized for communications transceivers. The pipelined architecture delivers low latency and deterministic sample timing across both channels, simplifying multi-channel synchronization in MIMO and phased-array systems.
Technical depth: the LTC2122CUK uses a calibrated pipelined core per channel with on-chip dither, achieving 70dBFS SNR and 90dBFS SFDR with input tones in the Nyquist zone. The JESD204B subclass 1 interface supports deterministic latency and supports 1 to 4 lanes per ADC, with link speeds up to 4.5Gbps per lane depending on configuration. The 7x7 mm QFN-48 package exposes a thermal pad for low-junction-rise operation.
Typical applications include multi-channel wireless communications receivers, multiband radar and phased-array digitizers, broadband data acquisition systems, and high-end test and measurement instrumentation. The dual-channel simultaneous-sampling capability is particularly valuable in diversity receivers and I/Q signal paths.
When designing with this part, ensure the JESD204B link parameters (L, M, F, K) match the receiving FPGA or ASIC SerDes, and provide a low-jitter clock with <300fs RMS jitter to preserve SNR. Decoupling on each supply pin must use a 0.1uF ceramic placed within 3 mm of the pin.
This page synthesizes distributor pricing, drop-in equivalents, and practical design notes not consolidated on the manufacturer datasheet.
Drop-in-Alternativen für LTC2122CUK – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.
Varianten dieser Serie
Modelle derselben Serie, die drop-in-kompatibel sind mit LTC2122CUK (gleiche Bauform und Footprint) – abweichend in SFDR, SNR, Package, Resolution, RoHS Status.
Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:
LTC2122CUK#PBF
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
LTC2122CUK#TRPBF
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
LTC2122IUK#PBF
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
LTC2122IUK
✅ Drop-In✓ Auf Lager
$81.5 / Stück
Datenblatt ansehen →LTC2122CUK#PBF-ND
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
AD9268BCPZ-125
✅ Drop-In📋 Referenzalternative (nicht im Katalog)
LTC2122CUK Grenzwerte & elektrische Eigenschaften
| Number of Channels | 2 (simultaneous sampling) |
| Auflösung | 14 bit |
| Abtastrate | 170 Msps per channel |
| Architecture | Pipelined |
| Input Bandwidth | 1.25 GHz |
| SNR | 70 dBFS |
| SFDR | 90 dBFS |
| Digital Output Interface | JESD204B (serial) |
| Number of Inputs | 2 |
| Package Type | 48-pin QFN (UK suffix, 7x7 mm) |
| Package Code | HVQCCN (QFN with exposed pad) |
| Montageart | Surface Mount |
| Operating Temperature Grade | Commercial (C suffix) |
| RoHS-Status | Compliant (PBF suffix) |
| Lead-Free / Halogen-Free | Yes (PBF suffix indicates lead-free) |
LTC2122CUK Pin-Konfiguration
| Pin 1 | GND — Ground reference (exposed pad also GND) |
| Pin 2 | INA+ — Channel A positive analog input |
| Pin 3 | INA- — Channel A negative analog input (complement) |
| Pin 4 | GND — Ground reference |
| Pin 5 | VCM — Common-mode voltage output for input biasing |
| Pin 6 | INB+ — Channel B positive analog input |
| Pin 7 | INB- — Channel B negative analog input (complement) |
| Pin 8 | GND — Ground reference |
| Pin 9 | VREF — Internal reference voltage bypass node |
| Pin 10 | SENSE — Reference configuration pin (internal/external) |
| Pin 11 | GND — Ground reference |
| Pin 12 | CLK+ — Sample clock positive input |
| Pin 13 | CLK- — Sample clock negative input (complement) |
| Pin 14 | GND — Ground reference |
| Pin 15 | OVDD — Output supply for digital I/O |
| Pin 16 | OGND — Output ground for digital I/O |
| Pin 17 | SDO — SPI serial data output (configuration) |
| Pin 18 | SCK — SPI serial clock (configuration) |
| Pin 19 | CS — SPI chip select (active low) |
| Pin 20 | RESET — Device reset (active low) |
| Pin 21 | SYNC — JESD204B synchronization request input |
| Pin 22 | SYSREF — JESD204B subclass 1 deterministic latency reference |
| Pin 23 | GND — Ground reference |
| Pin 24 | SERDOUT0+ — JESD204B lane 0 positive output |
| Pin 25 | SERDOUT0- — JESD204B lane 0 negative output |
| Pin 26 | OGND — Output ground for serializer |
| Pin 27 | OVDD — Serializer supply |
| Pin 28 | SERDOUT1+ — JESD204B lane 1 positive output (optional) |
| Pin 29 | SERDOUT1- — JESD204B lane 1 negative output (optional) |
| Pin 30 | OGND — Output ground |
| Pin 31 | NC — Not connected (per datasheet) |
| Pin 32 | NC — Not connected (per datasheet) |
| Pin 33 | NC — Not connected (per datasheet) |
| Pin 34 | NC — Not connected (per datasheet) |
| Pin 35 | VDD — Analog 1.8V supply |
| Pin 36 | GND — Ground reference |
| Pin 37 | VDD — Analog 1.8V supply |
| Pin 38 | GND — Ground reference |
| Pin 39 | VDD — Digital 1.8V supply |
| Pin 40 | GND — Ground reference |
| Pin 41 | VDD — Digital 1.8V supply |
| Pin 42 | GND — Ground reference |
| Pin 43 | OVDD — Output supply (1.8V) |
| Pin 44 | OGND — Output ground |
| Pin 45 | NC — Not connected (per datasheet) |
| Pin 46 | NC — Not connected (per datasheet) |
| Pin 47 | NC — Not connected (per datasheet) |
| Pin 48 | NC — Not connected (per datasheet) |
Typische Anwendungen
LTC2122CUK ist geeignet für 6 Anwendungs: Multi-Channel Wireless Communications Receiver, Phased-Array Radar and Beamforming Digitizer, Broadband Data Acquisition System, Software Defined Radio (SDR) Digitizer, Medical Imaging and Ultrasound Receiver, Test and Measurement Instrumentation.
Multi-Channel Wireless Communications Receiver
The LTC2122CUK is well suited to multi-channel wireless receivers because its dual 170Msps simultaneous-sampling channels digitize I/Q signal pairs or diversity paths in lockstep, preserving phase relationships critical for demodulation. With 70 dBFS SNR and 90 dBFS SFDR, the converter delivers clean capture of modulated waveforms in the presence of strong blockers, and the 1.25 GHz analog input bandwidth enables direct IF sampling of L-band or S-band signals without an external down-conversion mixer. The JESD204B serial output reduces PCB routing congestion between the ADC and the baseband FPGA, simplifying multi-channel MIMO receiver layouts where 8-16 ADCs must connect to a single FPGA. Design tip: use a low-jitter clock source below 300 fs RMS to preserve SNR, and configure the JESD204B link parameters (L, M, F, K) to match the FPGA SerDes capability.
Empfohlen
Phased-Array Radar and Beamforming Digitizer
In phased-array radar systems, the LTC2122CUK provides two simultaneous-sampling 14-bit 170Msps channels that capture I/Q baseband or IF signals from each antenna element with deterministic channel-to-channel latency via JESD204B subclass 1 synchronization. The 90 dBFS SFDR ensures that strong clutter and jammer signals do not desensitize weak target returns, and the wide 1.25 GHz input bandwidth allows direct sampling of IF frequencies well above the Nyquist limit, reducing analog filtering complexity. Multiple LTC2122CUK devices can be synchronized across an array using the SYSREF input, supporting coherent beamforming across hundreds of channels. Each device's 48-QFN 7x7 mm footprint allows dense PCB placement behind antenna elements. The exposed thermal pad must be soldered to a continuous ground pour to keep junction temperature low under sustained full-rate operation.
Empfohlen
Broadband Data Acquisition System
For broadband data acquisition systems, the LTC2122CUK delivers 14-bit 170Msps dual-channel digitizing capability in a compact 48-QFN package, suitable for oscilloscope front-ends, spectrum analyzer IF digitizers, and wideband software-defined radio capture cards. Its 1.25 GHz analog input bandwidth allows the system to capture signals in the first or second Nyquist zone, while 70 dBFS SNR provides sufficient dynamic range for general-purpose measurement. The JESD204B interface reduces board area by replacing 28+ parallel LVDS traces with one or two high-speed differential lanes, enabling dense multi-board stackups in modular instruments. Each ADC consumes moderate power at 170Msps, and the exposed pad provides a low-thermal-resistance path for sustained acquisition. Calibration dither can be enabled to improve small-signal linearity at the expense of slightly elevated noise floor.
Empfohlen
Software Defined Radio (SDR) Digitizer
Software-defined radio platforms benefit from the LTC2122CUK's combination of dual simultaneous-sampling channels, wide 1.25 GHz input bandwidth, and JESD204B serialized output to an FPGA for digital down-conversion. This enables direct sampling of HF, VHF, and UHF signals up through L-band with a single ADC pair, eliminating multiple analog mixer stages. The 14-bit resolution and 70 dBFS SNR are well matched to consumer and prosumer SDR applications, while the pipelined architecture provides deterministic sample timing required for coherent OFDM and CDMA demodulation. The 48-QFN package fits in compact USB-3 or Ethernet-attached SDR modules, and its moderate power dissipation allows fanless operation. Use the SYNC input to align channels when multiple LTC2122CUK devices are cascaded for wider instantaneous bandwidth.
Empfohlen
Medical Imaging and Ultrasound Receiver
In medical ultrasound receivers and other medical imaging front-ends, the LTC2122CUK's dual simultaneous-sampling channels digitize in-phase and quadrature echo returns with matched gain and phase characteristics, preserving beamformer accuracy across transducer arrays. The 14-bit 170Msps rate suits mid-frequency ultrasound probes (2-15 MHz harmonic bands) and the wide analog bandwidth allows digital beamforming of high-frequency signals. JESD204B serial output reduces cable harness complexity in cart-based imaging systems where the probe connects to the main unit via a long cable - fewer lanes mean less crosstalk and EMI susceptibility. The commercial temperature grade is suitable for indoor clinical environments; the LTC2122IUK variant extends to industrial/portable use cases. Strict ESD handling is required since the analog inputs are sensitive to discharge events.
Empfohlen
Test and Measurement Instrumentation
High-end oscilloscopes, spectrum analyzers, and arbitrary waveform generators use the LTC2122CUK as an IF or baseband digitizer block, leveraging its 14-bit resolution and 170Msps rate for accurate signal capture. The 90 dBFS SFDR ensures that harmonic and intermodulation measurements are not masked by converter distortion, supporting compliance testing of wireless transmitters. Dual channels enable vector signal analysis of I/Q modulated carriers, while the JESD204B interface allows multiple ADCs to feed a single FPGA for parallel test channels. The 48-QFN 7x7 mm footprint allows dense PCB placement in modular instruments with many acquisition channels, and the exposed pad provides a low-impedance thermal path for sustained capture at maximum sample rate. Configure the SYNC and SYSREF pins to deterministic-latency mode for synchronized multi-module acquisition.
Empfohlen
Zusammenfassung der empfohlenen Produkte
Technische Referenzdaten für LTC2122CUK – Vergleich, Designhinweise und Compliance-Informationen.
Auswahlhilfe
Vergleich mit Alternativen
| Parameter | Dieses Produkt | LTC2122CUK#PBF | LTC2122CUK#TRPBF | LTC2122IUK#PBF | LTC2122IUK | LTC2122CUK#PBF-ND | AD9268BCPZ-125 |
|---|---|---|---|---|---|---|---|
| Package | QFN-48 (UK, 7x7 mm) | QFN-48 (UK, 7x7 mm) | QFN-48 (UK, 7x7 mm) | QFN-48 (UK, 7x7 mm) | QFN-48 (UK, 7x7 mm) | QFN-48 (UK, 7x7 mm) | QFN-48 (7x7 mm family) |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit | 16 bit |
| Sampling Rate | 170 Msps | 170 Msps | 170 Msps | 170 Msps | 170 Msps | 170 Msps | 125 Msps |
| Channels | 2 (simultaneous) | 2 | 2 | 2 | 2 | 2 | 1 |
| Digital Output | JESD204B | JESD204B | JESD204B | JESD204B | JESD204B | JESD204B | LVDS / CMOS parallel |
| Temperature Grade | Commercial 0C to +70C | Commercial | Commercial | Industrial -40C to +85C | Industrial -40C to +85C | Commercial | Industrial |
| Lead-Free / RoHS | Yes (PBF) | Yes | Yes | Yes | Not specified | Yes | Yes |
Wichtigste Unterscheidungsmerkmale
- Dual simultaneous-sampling 14-bit channels at 170 Msps (vs. AD9268BCPZ-125)
- JESD204B serialized output reduces PCB routing complexity (vs. Parallel-LVDS ADCs)
- 1.25 GHz analog input bandwidth enables IF under-sampling (vs. Narrow-band ADCs (<500 MHz BW))
Designhinweise
Place each supply decoupling capacitor (0.1 uF ceramic) within 3 mm of its corresponding VDD pin, with a 10 uF bulk capacitor nearby on each supply rail. The exposed thermal pad must be soldered to a continuous ground pour on the top layer with at least 8 thermal vias to inner ground planes to keep junction temperature low under sustained full-rate acquisition. Maintain 50 ohm single-ended (or 100 ohm differential) controlled impedance on CLK+/- and analog input traces, and route JESD204B SERDOUT lanes as 100 ohm differential pairs with length matching within 0.5 mm across the entire link.
JESD204B SERDOUT+/- lanes operate at multi-gigabit data rates (up to 4.5 Gbps per lane in this family); use 100 ohm differential routing, avoid 90-degree bends, and place AC-coupling capacitors near the receiver side. The receiver FPGA or ASIC must have a SerDes capable of the configured line rate; mismatched line rate causes link training failures. Length-match lane-to-lane within 0.5 mm to preserve deterministic latency across multiple ADCs.
Do not exceed the maximum sample clock frequency (170 Msps) - higher rates cause SNR degradation. The SYSREF input must meet setup-and-hold timing relative to CLK+/- for deterministic JESD204B subclass 1 operation; misaligned SYSREF breaks multi-device synchronization. Avoid sharing analog input traces with digital outputs to prevent coupling into the analog front-end. Always configure the SENSE pin to match the desired reference (internal or external) before applying power to the analog inputs.
Compliance-Informationen
PBF suffix indicates lead-free and RoHS-compliant per Analog Devices ordering information. Industrial temperature LTC2122IUK#PBF variant is available for extended-temperature applications; AEC-Q100 automotive grade is not applicable for this part.
