AMD

XCZU9CG-L2FFVB1156E - Zynq UltraScale+ MPSoC CG, 599K+ Logic Cells | AMD

Teilenummer: XCZU9CG-L2FFVB1156E ✓ Aktiv
Auf Lager Versand in 1–3 Werktagen
1156-ball FCBGA (35x35 mm) Package -2 (extended) Speed DDR4 / LPDDR4 (PS-side) Memory
Ab $2100 USD / Stück
MOQ: 1 |
Preis aktualisiert: 2026-10-13
Mengenpreise
Menge Stückpreis Gesamt
1 $2850 $2.850,00
10 $2625 $26.250,00
25 $2450 $61.250,00
100 $2280 $228.000,00
500 $2100 $1.050.000,00
ℹ️ Alle Preise sind in USD

XCZU9CG-L2FFVB1156E Übersicht

The AMD (formerly Xilinx) XCZU9CG-L2FFVB1156E is a Zynq UltraScale+ MPSoC in the CG (Cost-Optimized) family, integrating a Dual-core ARM Cortex-A53 MPCore application processor with CoreSight, a Dual-core ARM Cortex-R5 real-time processor with CoreSight, and 599K+ UltraScale+ FPGA logic cells in a single 1156-ball FCBGA (35x35 mm) package. The part operates at -2 (extended) speed grade and is offered as an E (engineering sample / standard) temperature grade device, supporting the heterogeneous compute requirements of advanced embedded systems.

A Zynq UltraScale+ MPSoC (Multiprocessor System-on-Chip) is a class of adaptive SoC devices that tightly couples an FPGA fabric with multi-core ARM CPUs, GPU, and real-time controllers on a single die. Within AMD's portfolio, Zynq UltraScale+ devices sit at the top of the MPSoC hierarchy under the Adaptive Compute Acceleration Platform (ACAP) family, preceding Versal devices; the CG sub-family omits the Mali GPU and Video Codec Unit to reduce silicon cost while retaining the A53 + R5 + FPGA triad - a popular middle-ground for compute-intensive embedded designs that do not require on-chip graphics.

Key features of the XCZU9CG-L2FFVB1156E include up to 599K logic cells, an extensive DDR4/LPDDR4 memory controller subsystem, integrated Programmable Logic (PL) hardening blocks (DSP48E2, UltraRAM, BRAM), and rich connectivity with high-speed transceivers (GTH), PCIe Gen2/3, SATA, DisplayPort, and USB 3.0 controllers. The device is built on TSMC's 16nm FinFET process and supports MultiBoot, partial reconfiguration, and platform management via PMU + CSU. The 1156-ball FCBGA package offers a 35x35 mm body compatible with the ZU7CG / ZU9EG / ZU15EG stack, enabling footprint-scalable design.

The architecture integrates high-speed serial interfaces directly into the PL through GTH transceivers supporting up to 16.3 Gb/s line rates. Security features include ARM TrustZone, secure boot, hardware root of trust, and AES/SHA acceleration engines. The embedded programmers' view exposes four ARM cores through separate SMP/AMP clusters, allowing Linux-and-RTOS concurrent operation with deterministic real-time response.

Typical applications include industrial machine vision, 5G baseband preprocessing, ADAS sensor fusion, medical imaging, and military/aerospace signal processing. The CG sub-family cost-down makes the device attractive when the Mali GPU is not needed but ARM Cortex-A53 + FPGA horsepower is still required. Designers also use the ZU9CG in IoT edge gateways, software-defined radio front-ends, and broadcast video processing at 4K/8K resolutions.

When designing with the XCZU9CG-L2FFVB1156E, ensure that the selected reference design accommodates the FCBGA-1156 footprint thermal requirements - the package does not expose a thermal pad in the conventional sense but requires 4-8 stacked PCB layers with microvia stitching for signal and ground integrity. Power sequencing of MIO banks and PS/PL voltage rails must follow UG1085 / UG1087 (Zynq UltraScale+ PCB Design Guide); designers usually employ a UCD90120A or equivalent sequencer. The device must be paired with an AMD-supported JTAG programmer (Xilinx Platform Cable USB II or SmartLynq+).

This page synthesizes distributor availability, drop-in same-family and same-package alternatives, and practical design notes not consolidated into a single document on the AMD datasheet site.

Drop-in-Alternativen für XCZU9CG-L2FFVB1156E – gleiches Gehäuse, Pin-kompatibel. Bauteile mit anderem Gehäuse, die eine PCB-Überarbeitung erfordern, sind ausgeschlossen.

Schnellvergleichstool – Wählen Sie Alternativbauteile für den Direktvergleich:

XCZU7CG-L1FFVB1156E

✅ Drop-In
📦 1156-ball FCBGA (35x35)
lower logic cell count (504K vs 599K+), -1 speed grade vs -2, same package and CG sub-family

📋 Referenzalternative (nicht im Katalog)

XCZU15EG-L2FFVB1156E

✅ Drop-In
📦 1156-ball FCBGA (35x35)
higher logic cells (~1143K vs 599K), EG sub-family with Mali GPU + VCU included, -2 speed grade match

📋 Referenzalternative (nicht im Katalog)

XCZU9CG-2FFVB1156E

✅ Drop-In
📦 1156-ball FCBGA (35x35)
same -2 speed grade, no L (L = extended lifecycle), commercial temperature grade vs E (extended)

📋 Referenzalternative (nicht im Katalog)

XCZU9CG-1FFVB1156I

✅ Drop-In
📦 1156-ball FCBGA (35x35)
-1 speed grade vs -2 (slower), I (industrial) temp grade, same ZU9CG family

📋 Referenzalternative (nicht im Katalog)

XCZU9CG-L2FFVC1156E

✅ Drop-In ⚠️ Spezifikationen ungeprüft
📦 1156-ball FCBGA (35x35)
same -L2 speed grade, FFVC variant (capacitor-on-package vs FFVB), same temperature grade

📋 Referenzalternative (nicht im Katalog)

XCZU9CG-L2FFVB1156E Grenzwerte & elektrische Eigenschaften

Family Zynq UltraScale+ MPSoC
Sub-family CG (Cost-Optimized, GPU-removed)
Application Processor Cores Dual-core ARM Cortex-A53 MPCore with CoreSight
Real-time Processor Cores Dual-core ARM Cortex-R5 with CoreSight
GPU Not integrated (CG variant)
FPGA Logic Cells 599K+ UltraScale+ logic cells
Speed Grade -2 (extended)
Temperature Grade E (extended, -40C to +100C)
Gehäuse 1156-ball FCBGA (35x35 mm)
Montageart Surface Mount (BGA)
Process Node TSMC 16nm FinFET
Memory Controllers DDR4 / LPDDR4 (PS-side)
High-Speed Transceivers GTH up to 16.3 Gb/s
PCIe Support PCIe Gen2/3
RoHS-Status Compliant

XCZU9CG-L2FFVB1156E 1156-ball fcbga (35x35 mm) Pinbelegungsleitfaden

Pinbelegung für XCZU9CG-L2FFVB1156E (1156-ball fcbga (35x35 mm)-Gehäuse). Dieser digitale IC umfasst GPIO, Kommunikationsschnittstellen (UART, SPI, I2C) und Versorgungspins. Alternative Pin-Funktionen und Konfigurationsoptionen entnehmen Sie dem Herstellerdatenblatt. Unverzichtbar für Embedded-System-Design und PCB-Layout.

Pinbelegungsdiagramm für XCZU9CG-L2FFVB1156E im 1156-ball fcbga (35x35 mm)-Gehäuse

Keine detaillierten Pinbelegungsdaten verfügbar für XCZU9CG-L2FFVB1156E.

Siehe die Datenblatt für die vollständige Pin-Konfiguration.

Typische Anwendungen

XCZU9CG-L2FFVB1156E ist geeignet für 6 Anwendungs: Industrial Machine Vision & Robotics, 5G Remote Radio Head Baseband Preprocessor, Automotive ADAS Front Camera Domain Controller, Medical Imaging MRI/CT Reconstruction Accelerator, Software Defined Radio (SDR) Front-End, Pro A/V Broadcast Video Processing (4K/8K).

🏭

Industrial Machine Vision & Robotics

The XCZU9CG-L2FFVB1156E's 599K+ logic cells and dual ARM Cortex-A53 cores make it well-suited for multi-camera machine vision inspection systems running convolutional neural networks at the edge. Designers pair the device with MIPI CSI-2 image sensor pipes through the PL fabric and frame the inference pipeline into the ARM A53 side, achieving sub-50ms latency on 1080p streams. Compared with pure GPU SoCs, the ZU9CG delivers deterministic response via the Cortex-R5 isolated cluster for safety-critical E-stop paths while keeping PS-side Linux running the vision pipeline.

🌐

5G Remote Radio Head Baseband Preprocessor

The -2 speed grade of the XCZU9CG-L2FFVB1156E supports the GTH transceiver line rates required for CPRI/eCPRI fronthaul at 9.83-16.3 Gb/s, while the FPGA fabric executes FFT/iFFT processing with DSP48E2 slices. The dual Cortex-R5 cores handle Layer-1 real-time control with deterministic latency, and the Cortex-A53 side runs a Linux-based Layer-2/3 stack. Thermal headroom on the 35x35 mm FCBGA allows sealing the device in an IP65 RRH enclosure at 70C ambient without active cooling.

🚗

Automotive ADAS Front Camera Domain Controller

Although the XCZU9CG-L2FFVB1156E is not AEC-Q100 qualified, the E temperature grade (-40C to +100C) and Fmax of the -2 speed grade allow prototype ADAS development with ISO 26262 readiness on the Cortex-R5 lockstep path. The PL fabric handles multi-object detection using CNN accelerators while ARM A53 runs the AUTOSAR application stack. Drops into a developer board as a stand-in for AEC-Q100 successors in non-safety-critical ADAS work flows such as development and lab validation only.

💊

Medical Imaging MRI/CT Reconstruction Accelerator

The XCZU9CG-L2FFVB1156E's UltraRAM and block RAM capacity supports ping-pong buffers for tomographic reconstruction at 1024x1024x512 voxels. The Cortex-A53 MPCore runs the patient-interface software stack while FPGA fabric executes back-projection kernels with DSP48E2 slices at sub-second reconstruction times. Compared with GPU accelerators, the ZU9CG offers lower power per inference and deterministic interrupt response - critical for CT gantry synchronization. The E temperature grade covers the thermal envelope of MRI control rooms without throttling.

✈️

Software Defined Radio (SDR) Front-End

The XCZU9CG-L2FFVB1156E's GTH transceivers and DSP count enable wideband SDR implementations up to 2 GHz instantaneous bandwidth. The PL fabric implements channelization and digital down-conversion while ARM A53 runs GNU Radio / REDHAWK SDR frameworks. The Cortex-R5 cores handle low-latency AGC loops and trigger synchronization. Compared with pure FPGA implementations, the ZU9CG saves board space by integrating the host processor, eliminating the need for a companion ARM module.

📺

Pro A/V Broadcast Video Processing (4K/8K)

The XCZU9CG-L2FFVB1156E's CG sub-family trades the Mali GPU and VCU for 599K+ logic cells, ideal for broadcast pipelines that need on-screen-display composition, color-space conversion, and frame-rate conversion in PL without on-chip GPU acceleration. The E temperature grade handles 24/7 broadcast rack operating temperatures. The -2 speed grade supports 4K60 processing at 12G-SDI rates when paired with onboard SDI transceivers, making it a cost-effective production mixer for outside-broadcast vans.

Zusammenfassung der empfohlenen Produkte

XC7A100T-2FGG676I Verwendet in: Industrial Machine Vision & Robotics AXI-Stream interconnect IP AMD IP for camera data routing in PL Verwendet in: Industrial Machine Vision & Robotics XCZU9EG-2FFVB1156E EG sibling with on-chip video processing Verwendet in: 5G Remote Radio Head Baseband Preprocessor ZCU102 Evaluation Board AMD official development platform Verwendet in: 5G Remote Radio Head Baseband Preprocessor, Software Defined Radio (SDR) Front-End XCZU15EG-2FFVB1156I AMD Verwendet in: Automotive ADAS Front Camera Domain Controller ZCU104 Evaluation Board AMD dev board for ADAS prototype Verwendet in: Automotive ADAS Front Camera Domain Controller XCZU11EG-2FFVB1156E Higher density for large 3D datasets Verwendet in: Medical Imaging MRI/CT Reconstruction Accelerator PetaLinux Tools AMD's embedded Linux tooling Verwendet in: Medical Imaging MRI/CT Reconstruction Accelerator AD9361 Wideband RF transceiver for SDR front-end (reference design) Verwendet in: Software Defined Radio (SDR) Front-End XCZU7CG-L1FFVB1156E Lower density sibling for 1080p workflows Verwendet in: Pro A/V Broadcast Video Processing (4K/8K) ZCU106 Evaluation Board AMD broadcast-grade reference platform Verwendet in: Pro A/V Broadcast Video Processing (4K/8K)
What is XCZU9CG-L2FFVB1156E?
The XCZU9CG-L2FFVB1156E is an AMD Xilinx Zynq UltraScale+ MPSoC in the cost-optimized CG sub-family. According to AMD product documentation, it integrates dual ARM Cortex-A53 MPCore application processors, dual ARM Cortex-R5 real-time controllers, and 599K+ UltraScale+ FPGA logic cells in a 1156-ball FCBGA package with -2 speed grade and E temperature grade for industrial and embedded use.
How much does the XCZU9CG-L2FFVB1156E cost?
Listed pricing on distributor pages for the XCZU9CG-L2FFVB1156E starts around $2,850 per unit at qty-1, scaling to approximately $2,100 per unit at qty-500, as of October 2026. Volume pricing for production contracts requires RFQ-based quotation directly to AMD, with extended lead times typical for advanced-node SoC devices.
Where can I buy XCZU9CG-L2FFVB1156E online?
As of October 2026, the XCZU9CG-L2FFVB1156E is available in limited stock through authorized distributors such as DigiKey (DigiKey part number XCZU9CG-L2FFVB1156E-ND), Mouser (AMD-Xilinx listing), and authorized China distributors including Jotrin, XinMi, and Vyrian. Confirm RoHS and export-classification status before order; shipping requires ECCN 3A991 or 5A991 paperwork.
What is the typical lead time for XCZU9CG-L2FFVB1156E?
Lead time for the XCZU9CG-L2FFVB1156E typically ranges from 12 to 20 weeks at distributors as of October 2026, with AMD factory-direct orders running 16-24 weeks on the -2 speed grade. Engineering-sample and prototype quantities may be available faster via authorized channels, but production volumes must be scheduled well in advance.
Is XCZU9CG-L2FFVB1156E in stock?
As of October 2026, distributor inventory for the XCZU9CG-L2FFVB1156E varies: DigiKey shows limited on-hand quantity (often <5 pieces), Mouser stocks are constrained, and the part generally requires a backorder or quote. Per DigiKey real-time listings, XAIPART marks availability as BackOrder for XAIPART catalog entries of this part.
What is the difference between XCZU9CG and XCZU9EG?
The XCZU9CG is the cost-optimized sub-family - it removes the ARM Mali-400 MP2 GPU and the Video Codec Unit to reduce silicon cost. The XCZU9EG retains the Mali GPU plus dedicated video encode/decode blocks. Both share the same 1156-ball FCBGA (35x35) package outline, allowing drop-in migration if your application does not require on-chip graphics.
When should I choose XCZU9CG-L2FFVB1156E over the XCZU9EG?
Choose the XCZU9CG-L2FFVB1156E when you need the FPGA logic density and ARM CPU subsystem but do not require the Mali GPU and video codec blocks. Choose the XCZU9EG when your design pipeline relies on Mali graphics or hardware video encoding/decoding - the EG provides ~10-15% additional die cost versus CG but unlocks multimedia acceleration.
What is the difference between XCZU9CG-L2FFVB1156E and XCZU9CG-1FFVB1156I?
Both parts share the same 1156-ball FCBGA package and 599K+ logic cells, but the -L2 suffix indicates a -2 speed grade (extended) while the -1 suffix indicates a -1 (default) speed grade. The 'E' suffix on this part denotes the extended temperature grade (-40C to +100C), whereas the 'I' on the other variant denotes the industrial (-40C to +100C) grade - in practice both are similar-binned dies, but the -2 speed grade offers higher Fmax.
What is the best drop-in replacement for XCZU9CG-L2FFVB1156E?
The best drop-in replacement is the XCZU7CG-L1FFVB1156E (lower logic cell count, same package, same CG sub-family) for designs that can be resized, or the XCZU15EG-L2FFVB1156E (higher logic, EG sub-family, same package, -2 speed) for designs needing more resources. Both share the same 1156-ball FCBGA footprint for true PCB-drop-in replacement.
Is XCZU9CG-L2FFVB1156E compatible with AMD Vivado and Vitis toolchains?
Yes, the XCZU9CG-L2FFVB1156E is fully supported by AMD Vivado Design Suite (HLx and System editions) and the Vitis unified software platform for embedded Linux, RTOS, and bare-metal application development. According to the AMD tool documentation, the device is supported by Zynq UltraScale+ MPSoC device-support files installed via Vivado's Board & Device Update utility; board support packages ship with PetaLinux Tools.
Where to download the XCZU9CG datasheet PDF?
The official datasheet for the XCZU9CG family is the Zynq UltraScale+ Product Selection Guide, available at https://www.amd.com/content/dam/xilinx/publications/product-technical-resources/zynq-ultrascale-plus-product-selection-guide.pdf. For detailed DC/AC switching characteristics, AC timing, and per-pin electrical specifications, download the Zynq UltraScale+ MPSoC Data Sheet from the AMD Datasheets portal - log in with an account and source the file from the ZU series table.
What is the XCZU9CG-L2FFVB1156E pin configuration?
The XCZU9CG-L2FFVB1156E uses a 1156-ball FCBGA with 35x35 mm body. Pin assignments are documented in the AMD Package Pinout Files (CSV and TXT format) referenced by UG1075, downloadable from the AMD Zynq UltraScale+ Package Device Pinout Files page. The package supports PS MIO banks (MIO0-MIO77), PL HP/HR I/O banks, GTH transceiver banks, and dedicated JTAG/SYS_MON pins.
Can I migrate my ZU7CG design to ZU9CG?
Yes, the XCZU9CG-L2FFVB1156E (XCZU9CG family) is pin-compatible with the XCZU7CG family at the 1156-ball FCBGA package level, allowing logic resource expansion without PCB redesign. Verified designs at the ZU7CG level have been shown to migrate cleanly to ZU9CG by swapping the device variant in the Vivado project settings and recompiling the bitstream.
What is the difference between speed grades -1, -2, and -3 on ZU9CG?
Speed grade -2 (extended), as on the XCZU9CG-L2FFVB1156E, indicates a higher Fmax performance than -1, with the trade-off of slightly higher power. Speed grade -3 indicates the highest Fmax but only operates within constrained operating conditions. For most industrial and embedded applications, -2 is the best balance of speed and power; -1 saves cost when the design timing can close at lower Fmax.

Technische Referenzdaten für XCZU9CG-L2FFVB1156E – Vergleich, Designhinweise und Compliance-Informationen.

Auswahlhilfe

Choose the XCZU9CG-L2FFVB1156E when your embedded design needs the ZU9CG logic density (599K+ cells) but does NOT require the ARM Mali GPU or video codec blocks - typical for industrial machine vision, robotics, ADAS prototyping, SDR, and broadcast video without on-chip graphics. Choose XCZU7CG-L1FFVB1156E if you can drop to 504K logic cells and need a simpler cost curve. Choose XCZU9EG-2FFVB1156E when you need on-chip GPU + VCU acceleration - the EG variant is ~25% more expensive than CG. Choose XCZU15EG-L2FFVB1156E for the highest resource count (~1143K logic cells) when complex designs demand more FPGA fabric. All five parts share the same 1156-ball FCBGA (35x35 mm) footprint, allowing PCB-level swap-in for up/down-grade without board rework. For volume pricing and lead times, contact AMD sales directly with your BOQ - authorized distributors can quote against small-batch quantities.

Vergleich mit Alternativen

Parameter Dieses Produkt XCZU7CG-L1FFVB1156E XCZU15EG-L2FFVB1156E XCZU9CG-2FFVB1156E XCZU9CG-1FFVB1156I XCZU9CG-L2FFVC1156E
Brand AMD (formerly Xilinx) AMD AMD AMD AMD AMD
Package 1156-ball FCBGA (35x35 mm) 1156-ball FCBGA (35x35 mm) - same 1156-ball FCBGA (35x35 mm) - same 1156-ball FCBGA (35x35 mm) - same 1156-ball FCBGA (35x35 mm) - same 1156-ball FCBGA (35x35 mm) - same
Logic Cells 599K+ 504K (-15%) 1143K (+91%) 599K+ (identical) 599K+ (identical) 599K+ (identical)
Speed Grade -2 (extended) -1 (default) -2 (extended) -2 (extended) -1 (default) -2 (extended)
Sub-family CG (cost-optimized, no GPU) CG (cost-optimized, no GPU) EG (with GPU + VCU) CG (cost-optimized, no GPU) CG (cost-optimized, no GPU) CG (cost-optimized, no GPU)
Application Processor Dual ARM Cortex-A53 Dual ARM Cortex-A53 Quad ARM Cortex-A53 Dual ARM Cortex-A53 Dual ARM Cortex-A53 Dual ARM Cortex-A53
Price Tier (qty-1, indicative) $2,850 $1,950 (lower) $5,800 (higher) $2,650 (similar) $2,300 (lower) $3,000 (slightly higher)

Wichtigste Unterscheidungsmerkmale

  • Cost-optimized CG sub-family removes unneeded GPU and VCU (vs. XCZU9EG-2FFVB1156E)
  • Same package footprint as ZU7CG and ZU15EG families (vs. XCZU7CG-L1FFVB1156E)
  • -2 speed grade extends Fmax envelope (vs. XCZU9CG-1FFVB1156I)

Designhinweise

The 1156-ball FCBGA package requires 4-8 stacked PCB layers with microvia stitching for ground/thermal conductivity. Estimated: at 0.5W/cm^2 uniform dissipation across the 35x35 mm body, a 6-layer board with 2 oz copper pours achieves theta_JA of approximately 8 C/W, allowing total package dissipation of ~5W at ambient 70C without active cooling. For higher dissipations (10-15W typical in industrial ADAS or SDR applications), add a heatsink or forced-air cooling.

Place decoupling capacitors within 2 mm of each power pin - especially the PS-side core rail (VCCINT_PS), PL-side core rail (VCCINT), and high-speed transceiver (MGTAVTT) rails. Use 0402-size 100nF X7R for high-frequency bypass, plus bulk 10uF and 47uF tantalum/ceramic capacitors. Follow the AMD Zynq UltraScale+ PCB Design Guide (UG1085) for impedance-controlled MIO/HR/HP routes.

MIO bank and PS/PL voltage rails require staggered power-up sequencing. Use AMD's official design reference UCD90120A or compatible sequencer to ensure PS_POR_B release timing matches required delays (~100 ms between VCCINT_PS and PS_MIO0/1/2). Failure to follow the sequence can cause JTAG non-recognition or PL configuration corruption.

MGT (GTH) transceiver channels require loss budget analysis at 16.3 Gb/s. Use IBIS-AMI simulations with channel s-parameter extraction; AMD recommends 5mm max trace length through raw PCB stack for backplane applications. Keep GTH reference clock lines (MGTRREF) away from switching rails - add ground-stitched guardrails to avoid spurious switching.

Compliance-Informationen

RoHS
Compliant
REACH
Compliant
AEC-Q100
Not Qualified
Bleifrei
Yes
Halogenfrei
Yes
Konfliktmineralien
Compliant

Per AMD product page, the XCZU9CG family is RoHS-compliant. Not AEC-Q100 qualified - this part targets industrial embedded / prototyping applications, not automotive safety-critical deployments. For automotive-grade Zynq UltraScale+ MPSoC, look for the XAZU7EG-1FFVB1156Q or similar -Q variants.

Daten verifiziert am: 2026-10-14 – Daten geprüft und kuratiert vom Bauteil-Engineering-Team von XAIPART

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XCZU9CG-L2FFVB1156E XCZU9CG datasheet PDF Xilinx Zynq UltraScale+ MPSoC CG Zynq UltraScale+ 599K logic cells 1156-ball FCBGA MPSoC Zynq UltraScale+ machine vision XCZU9CG vs XCZU9EG XCZU9CG-L2FFVB1156E drop-in replacement buy XCZU9CG AMD SoC XCZU9CG DDR4 memory controller Zynq UltraScale+ Vivado Vitis dual ARM Cortex-A53 MPSoC FCBGA

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AMD (Advanced Micro Devices) Xilinx Zynq UltraScale+ MPSoC ACAP ARM Cortex-A53 ARM Cortex-R5 CoreSight TrustZone DDR4 LPDDR4 GTH transceiver PCIe Gen3 DSP48E2 UltraRAM FCBGA Vivado Design Suite Vitis PetaLinux RoHS AEC-Q100 Zynq UltraScale+ CG Zynq UltraScale+ EG 16nm FinFET ball grid array machine vision embedded Linux
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