EP1810JC-35 vs EP1810GM883 Comparación
Comparación detallada lado a lado de EP1810JC-35 por Intel y EP1810GM883 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810JC-35 | EP1810GM883 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $5,48 | $175,00 |
| Device Family | Classic EPLD (EP1810) | — |
| Device Type | UV-Erasable Complex PLD (UV PLD / CPLD) | UV-Erasable Programmable Logic Device (EPLD) |
| Number of Macrocells | 48 | — |
| Propagation Delay (tpd) | 35 ns (max) | 45 ns (max) |
| Frecuencia de reloj máxima | [DATA_NEEDED: fmax for this speed grade] | — |
| Process Technology | CMOS | CMOS, UV-erasable |
| Supply Voltage (Vcc) | 5 V (nominal) | 4.5 V to 5.5 V (nominal 5 V) |
| Maximum Supply Voltage | 5.25 V (per distributor listing) | — |
| Package Type | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) | — |
| Number of Terminals | 68 | — |
| Terminal Form | J-Bend | — |
| Rango de temperatura de funcionamiento | 0°C to 70°C (Commercial) | — |
| Temperature Grade | Commercial | — |
| Erasure Method | UV (quartz-windowed ceramic package) | — |
| Estado RoHS | Compliant (per Altera listing) | [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data] |
| Lead-Free Status | Lead-free (per distributor listing) | — |
| Tipo de montaje | Surface Mount (J-Lead) | Through-Hole (PGA socket) |
| Logic Architecture | Programmable AND/OR array with macrocell outputs | — |
| Family | — | Classic EPLD (EP1810 series) |
| Macrocells | — | 48 |
| Dedicated Inputs | — | 12 |
| User I/O Pins | — | 48 |
| Total Terminals | — | 68 |
| Global Clocks | — | 4 |
| Maximum Toggle Frequency (fmax) | — | [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade] |
| Encapsulado | — | 68-Pin Ceramic Pin Grid Array (PGA) |
| Temperatura de funcionamiento | — | -55C to +125C (MIL-STD-883 Class B) |
| Screening | — | MIL-STD-883 Class B (suffix '883' denotes MIL processing) |
| Lead-Free | — | [DATA_NEEDED: military 883B screened parts commonly use SnPb finish] |