EP1810JC-35 vs EP1810GM883 비교

다음의 상세 나란히 비교: EP1810JC-35 제조: Intel 및 EP1810GM883 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EP1810JC-35 EP1810GM883
브랜드 Intel Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete Obsolete
재고 상태 In Stock In Stock
단가 (USD) $5.48 $175.00
Device Family Classic EPLD (EP1810) —
Device Type UV-Erasable Complex PLD (UV PLD / CPLD) UV-Erasable Programmable Logic Device (EPLD)
Number of Macrocells 48 —
Propagation Delay (tpd) 35 ns (max) 45 ns (max)
최대 클록 주파수 [DATA_NEEDED: fmax for this speed grade] —
Process Technology CMOS CMOS, UV-erasable
Supply Voltage (Vcc) 5 V (nominal) 4.5 V to 5.5 V (nominal 5 V)
Maximum Supply Voltage 5.25 V (per distributor listing) —
Package Type CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) —
Number of Terminals 68 —
Terminal Form J-Bend —
동작 온도 범위 0°C to 70°C (Commercial) —
Temperature Grade Commercial —
Erasure Method UV (quartz-windowed ceramic package) —
RoHS 상태 Compliant (per Altera listing) [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data]
Lead-Free Status Lead-free (per distributor listing) —
실장 유형 Surface Mount (J-Lead) Through-Hole (PGA socket)
Logic Architecture Programmable AND/OR array with macrocell outputs —
Family — Classic EPLD (EP1810 series)
Macrocells — 48
Dedicated Inputs — 12
User I/O Pins — 48
Total Terminals — 68
Global Clocks — 4
Maximum Toggle Frequency (fmax) — [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade]
패키지 — 68-Pin Ceramic Pin Grid Array (PGA)
동작 온도 — -55C to +125C (MIL-STD-883 Class B)
Screening — MIL-STD-883 Class B (suffix '883' denotes MIL processing)
Lead-Free — [DATA_NEEDED: military 883B screened parts commonly use SnPb finish]

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