EP1810JC-35 vs EP1810GM883 Comparaison
Comparaison détaillée côte à côte de EP1810JC-35 par Intel et EP1810GM883 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1810JC-35 | EP1810GM883 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $5,48 | $175,00 |
| Device Family | Classic EPLD (EP1810) | — |
| Device Type | UV-Erasable Complex PLD (UV PLD / CPLD) | UV-Erasable Programmable Logic Device (EPLD) |
| Number of Macrocells | 48 | — |
| Propagation Delay (tpd) | 35 ns (max) | 45 ns (max) |
| Fréquence d'horloge maximale | [DATA_NEEDED: fmax for this speed grade] | — |
| Process Technology | CMOS | CMOS, UV-erasable |
| Supply Voltage (Vcc) | 5 V (nominal) | 4.5 V to 5.5 V (nominal 5 V) |
| Maximum Supply Voltage | 5.25 V (per distributor listing) | — |
| Package Type | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) | — |
| Number of Terminals | 68 | — |
| Terminal Form | J-Bend | — |
| Plage de température de fonctionnement | 0°C to 70°C (Commercial) | — |
| Temperature Grade | Commercial | — |
| Erasure Method | UV (quartz-windowed ceramic package) | — |
| Statut RoHS | Compliant (per Altera listing) | [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data] |
| Lead-Free Status | Lead-free (per distributor listing) | — |
| Type de montage | Surface Mount (J-Lead) | Through-Hole (PGA socket) |
| Logic Architecture | Programmable AND/OR array with macrocell outputs | — |
| Family | — | Classic EPLD (EP1810 series) |
| Macrocells | — | 48 |
| Dedicated Inputs | — | 12 |
| User I/O Pins | — | 48 |
| Total Terminals | — | 68 |
| Global Clocks | — | 4 |
| Maximum Toggle Frequency (fmax) | — | [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade] |
| Boîtier | — | 68-Pin Ceramic Pin Grid Array (PGA) |
| Température de fonctionnement | — | -55C to +125C (MIL-STD-883 Class B) |
| Screening | — | MIL-STD-883 Class B (suffix '883' denotes MIL processing) |
| Lead-Free | — | [DATA_NEEDED: military 883B screened parts commonly use SnPb finish] |