EP1810JC-35 vs EP1810GM883 比較

詳細な並列比較: EP1810JC-35 メーカー: Intel および EP1810GM883 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EP1810JC-35 EP1810GM883
ブランド Intel Altera
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 Obsolete Obsolete
在庫状況 In Stock In Stock
単価(USD) $5.48 $175.00
Device Family Classic EPLD (EP1810) —
Device Type UV-Erasable Complex PLD (UV PLD / CPLD) UV-Erasable Programmable Logic Device (EPLD)
Number of Macrocells 48 —
Propagation Delay (tpd) 35 ns (max) 45 ns (max)
最大クロック周波数 [DATA_NEEDED: fmax for this speed grade] —
Process Technology CMOS CMOS, UV-erasable
Supply Voltage (Vcc) 5 V (nominal) 4.5 V to 5.5 V (nominal 5 V)
Maximum Supply Voltage 5.25 V (per distributor listing) —
Package Type CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) —
Number of Terminals 68 —
Terminal Form J-Bend —
動作温度範囲 0°C to 70°C (Commercial) —
Temperature Grade Commercial —
Erasure Method UV (quartz-windowed ceramic package) —
RoHS ステータス Compliant (per Altera listing) [DATA_NEEDED: hermetic ceramic PGA is typically non-RoHS due to lead-bearing solder/finish; not confirmed in source data]
Lead-Free Status Lead-free (per distributor listing) —
実装タイプ Surface Mount (J-Lead) Through-Hole (PGA socket)
Logic Architecture Programmable AND/OR array with macrocell outputs —
Family — Classic EPLD (EP1810 series)
Macrocells — 48
Dedicated Inputs — 12
User I/O Pins — 48
Total Terminals — 68
Global Clocks — 4
Maximum Toggle Frequency (fmax) — [DATA_NEEDED: fmax value not in source data; Classic EPLD family typical 35-80 MHz depending on grade]
パッケージ — 68-Pin Ceramic Pin Grid Array (PGA)
動作温度 — -55C to +125C (MIL-STD-883 Class B)
Screening — MIL-STD-883 Class B (suffix '883' denotes MIL processing)
Lead-Free — [DATA_NEEDED: military 883B screened parts commonly use SnPb finish]

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