EP1810JC-45 vs EP1810JC-35 Comparación
Comparación detallada lado a lado de EP1810JC-45 por Altera y EP1810JC-35 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1810JC-45 | EP1810JC-35 |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $21,10 | $5,48 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP1810 (Classic EPLD Family) | — |
| Macrocells | 48 | — |
| Equivalent Gates | 2100 gates | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 | — |
| Total User I/O | 60 | — |
| Propagation Delay (tpd) | 45 ns | 35 ns (max) |
| Frecuencia de reloj máxima | 33.3 MHz | [DATA_NEEDED: fmax for this speed grade] |
| Technology | CMOS, UV-erasable | — |
| Maximum Supply Voltage | 5.25 V | 5.25 V (per distributor listing) |
| Encapsulado | PLCC-68 (QCCJ, J-Lead, windowed ceramic) | — |
| Recuento de pines | 68 | — |
| Package Code | QCCJ | — |
| Temperature Grade | Commercial | Commercial |
| Tipo de montaje | Surface Mount | Surface Mount (J-Lead) |
| Estado RoHS | [DATA_NEEDED: RoHS compliance not stated in verified data] | Compliant (per Altera listing) |
| Device Family | — | Classic EPLD (EP1810) |
| Device Type | — | UV-Erasable Complex PLD (UV PLD / CPLD) |
| Number of Macrocells | — | 48 |
| Process Technology | — | CMOS |
| Supply Voltage (Vcc) | — | 5 V (nominal) |
| Package Type | — | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) |
| Number of Terminals | — | 68 |
| Terminal Form | — | J-Bend |
| Rango de temperatura de funcionamiento | — | 0°C to 70°C (Commercial) |
| Erasure Method | — | UV (quartz-windowed ceramic package) |
| Lead-Free Status | — | Lead-free (per distributor listing) |
| Logic Architecture | — | Programmable AND/OR array with macrocell outputs |