EP1810JC-45 vs EP1810JC-35 比較
詳細な並列比較: EP1810JC-45 メーカー: Altera および EP1810JC-35 メーカー: Intel。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EP1810JC-45 | EP1810JC-35 |
|---|---|---|
| ブランド | Altera | Intel |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | NRND | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $21.10 | $5.48 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP1810 (Classic EPLD Family) | — |
| Macrocells | 48 | — |
| Equivalent Gates | 2100 gates | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 48 | — |
| Total User I/O | 60 | — |
| Propagation Delay (tpd) | 45 ns | 35 ns (max) |
| 最大クロック周波数 | 33.3 MHz | [DATA_NEEDED: fmax for this speed grade] |
| Technology | CMOS, UV-erasable | — |
| Maximum Supply Voltage | 5.25 V | 5.25 V (per distributor listing) |
| パッケージ | PLCC-68 (QCCJ, J-Lead, windowed ceramic) | — |
| ピン数 | 68 | — |
| Package Code | QCCJ | — |
| Temperature Grade | Commercial | Commercial |
| 実装タイプ | Surface Mount | Surface Mount (J-Lead) |
| RoHS ステータス | [DATA_NEEDED: RoHS compliance not stated in verified data] | Compliant (per Altera listing) |
| Device Family | — | Classic EPLD (EP1810) |
| Device Type | — | UV-Erasable Complex PLD (UV PLD / CPLD) |
| Number of Macrocells | — | 48 |
| Process Technology | — | CMOS |
| Supply Voltage (Vcc) | — | 5 V (nominal) |
| Package Type | — | CQCC-68 (Ceramic J-Lead Chip Carrier, QCCJ) |
| Number of Terminals | — | 68 |
| Terminal Form | — | J-Bend |
| 動作温度範囲 | — | 0°C to 70°C (Commercial) |
| Erasure Method | — | UV (quartz-windowed ceramic package) |
| Lead-Free Status | — | Lead-free (per distributor listing) |
| Logic Architecture | — | Programmable AND/OR array with macrocell outputs |