EP1810LC-35 vs EP1810LC-25 Comparación
Comparación detallada lado a lado de EP1810LC-35 por Rochester Electronics y EP1810LC-25 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Rochester Electronics
EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera
EP1810LC-35 ⚠ Última compra
Comparación de especificaciones
| Parámetro | EP1810LC-35 | EP1810LC-25 |
|---|---|---|
| Marca | Rochester Electronics | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $49,20 | $8,40 |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Series | Classic EP1810 | — |
| Macrocells | 48 | 48 |
| Equivalent Gates | 900 usable / 2100 equivalent | — |
| Maximum Operating Frequency | 28.6 MHz | — |
| Propagation Delay (tpd) | 35 ns (max, '-35' speed grade) | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V (TTL-compatible) |
| Technology | CMOS, UV-erasable EPROM | CMOS EPLD (erasable programmable logic device) |
| Encapsulado | 68-pin PLCC (J-Lead) | 68-pin JLCC (J-leaded ceramic chip carrier) |
| Tipo de montaje | Surface Mount (socketable) | Surface Mount |
| Temperatura de funcionamiento | 0C to +70C (commercial) | [DATA_NEEDED: temperature grade for LC package] |
| I/O Pins | [DATA_NEEDED: I/O count exact] | 48 |
| Configuration Method | UV-erase + EPROM programmer | — |
| Programmable Interconnect | Centralized Programmable Interconnect Array (PIA) | Global + Local buses |
| Development Tool (legacy) | MAX+PLUS II / A+PLUS | — |
| Estado RoHS | [DATA_NEEDED] | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] |
| Lead-Free | [DATA_NEEDED] | — |
| Product Family | — | Altera Classic EPLD |
| Part Number | — | EP1810LC-25 |
| Propagation Delay (tPD) | — | 25 ns |
| Dedicated Inputs | — | 12 |
| External Clock Inputs | — | 4 |
| Operating Mode | — | Turbo-only (no slow-power mode) |
| Package Code | — | LC = 68-pin JLCC |
| Programming Method | — | Altera Classic programmer + MAX+PLUS II legacy flow |
| Estado del ciclo de vida | — | Obsolete (legacy Altera Classic family) |