EP1810LC-35 vs EP1810LC-25 비교
다음의 상세 나란히 비교: EP1810LC-35 제조: Rochester Electronics 및 EP1810LC-25 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Rochester Electronics
EP1810LC-35 - 48-Macrocell Classic EPLD, 35ns, PLCC-68 | Rochester/Altera
EP1810LC-35 ⚠ 최종 구매
사양 비교
| 파라미터 | EP1810LC-35 | EP1810LC-25 |
|---|---|---|
| 브랜드 | Rochester Electronics | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | 최종 구매 | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $49.20 | $8.40 |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Series | Classic EP1810 | — |
| Macrocells | 48 | 48 |
| Equivalent Gates | 900 usable / 2100 equivalent | — |
| Maximum Operating Frequency | 28.6 MHz | — |
| Propagation Delay (tpd) | 35 ns (max, '-35' speed grade) | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V (TTL-compatible) |
| Technology | CMOS, UV-erasable EPROM | CMOS EPLD (erasable programmable logic device) |
| 패키지 | 68-pin PLCC (J-Lead) | 68-pin JLCC (J-leaded ceramic chip carrier) |
| 실장 유형 | Surface Mount (socketable) | Surface Mount |
| 동작 온도 | 0C to +70C (commercial) | [DATA_NEEDED: temperature grade for LC package] |
| I/O Pins | [DATA_NEEDED: I/O count exact] | 48 |
| Configuration Method | UV-erase + EPROM programmer | — |
| Programmable Interconnect | Centralized Programmable Interconnect Array (PIA) | Global + Local buses |
| Development Tool (legacy) | MAX+PLUS II / A+PLUS | — |
| RoHS 상태 | [DATA_NEEDED] | [DATA_NEEDED: RoHS compliance not confirmed in legacy datasheet] |
| Lead-Free | [DATA_NEEDED] | — |
| Product Family | — | Altera Classic EPLD |
| Part Number | — | EP1810LC-25 |
| Propagation Delay (tPD) | — | 25 ns |
| Dedicated Inputs | — | 12 |
| External Clock Inputs | — | 4 |
| Operating Mode | — | Turbo-only (no slow-power mode) |
| Package Code | — | LC = 68-pin JLCC |
| Programming Method | — | Altera Classic programmer + MAX+PLUS II legacy flow |
| 수명 주기 상태 | — | Obsolete (legacy Altera Classic family) |