EP1M120F484C8ES vs EP1M120F484I6M Comparación
Comparación detallada lado a lado de EP1M120F484C8ES por Intel y EP1M120F484I6M por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1M120F484C8ES | EP1M120F484I6M |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $119,40 | $325,00 |
| Family | ACEX 1M | Mercury (EP1M) |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements / Gates | 120,000 (120K gates) | — |
| Embedded Logic Cells (EABs) | 4,800 | — |
| User I/O Pins | 303 | — |
| Encapsulado | 484-ball FineLine BGA | — |
| Speed Grade | C8 (-8 speed bin) | -6 (slowest Mercury timing bin) |
| Sample Grade | ES (Engineering Sample) | — |
| Process Technology | 0.18 µm CMOS, SRAM-based | — |
| Embedded RAM | ~104 Kbits across 12 RAM blocks | — |
| PLLs | 4 enhanced PLLs | — |
| I/O Standards | LVTTL, LVCMOS, True-LVDS, PCI | LVTTL, LVCMOS, SSTL, HSTL, LVDS |
| Operating Voltage (Core) | [DATA_NEEDED: core VCC range] | — |
| MultiVolt I/O Support | 1.5 V / 2.5 V / 3.3 V / 5.0 V tolerant | — |
| Configuration Method | SRAM bitstream, JTAG/serial | — |
| Temperatura de funcionamiento | [DATA_NEEDED: industrial/commercial grade temp range] | — |
| Estado RoHS | [DATA_NEEDED] | Compliant (M revision) |
| Tipo de montaje | Surface Mount (BGA) | — |
| Logic Elements | — | 120,000 |
| System Gates | — | 480,000 (typical) |
| LABs / CLBs | — | 303 |
| Flip-Flops | — | 49,152 |
| Embedded Memory (Bits) | — | 4,800 Kb (480 Kbits) |
| Package Type | — | 484-Ball FCBGA |
| Package Code | — | BGA, 484 balls, Fine-pitch |
| Package Shape | — | Square |
| Terminal Form | — | Ball |
| Temperature Grade | — | Industrial |
| Tensión de alimentación | — | 1.5 V core / 3.3 V aux (per Mercury datasheet) |
| Clock Management | — | PLLs (per Mercury family) |
| Boundary-Scan | — | IEEE 1149.1 / JTAG |