EP1M120F484C8ES vs EP1M120F484I6M Comparaison
Comparaison détaillée côte à côte de EP1M120F484C8ES par Intel et EP1M120F484I6M par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP1M120F484C8ES | EP1M120F484I6M |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $119,40 | $325,00 |
| Family | ACEX 1M | Mercury (EP1M) |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements / Gates | 120,000 (120K gates) | — |
| Embedded Logic Cells (EABs) | 4,800 | — |
| User I/O Pins | 303 | — |
| Boîtier | 484-ball FineLine BGA | — |
| Speed Grade | C8 (-8 speed bin) | -6 (slowest Mercury timing bin) |
| Sample Grade | ES (Engineering Sample) | — |
| Process Technology | 0.18 µm CMOS, SRAM-based | — |
| Embedded RAM | ~104 Kbits across 12 RAM blocks | — |
| PLLs | 4 enhanced PLLs | — |
| I/O Standards | LVTTL, LVCMOS, True-LVDS, PCI | LVTTL, LVCMOS, SSTL, HSTL, LVDS |
| Operating Voltage (Core) | [DATA_NEEDED: core VCC range] | — |
| MultiVolt I/O Support | 1.5 V / 2.5 V / 3.3 V / 5.0 V tolerant | — |
| Configuration Method | SRAM bitstream, JTAG/serial | — |
| Température de fonctionnement | [DATA_NEEDED: industrial/commercial grade temp range] | — |
| Statut RoHS | [DATA_NEEDED] | Compliant (M revision) |
| Type de montage | Surface Mount (BGA) | — |
| Logic Elements | — | 120,000 |
| System Gates | — | 480,000 (typical) |
| LABs / CLBs | — | 303 |
| Flip-Flops | — | 49,152 |
| Embedded Memory (Bits) | — | 4,800 Kb (480 Kbits) |
| Package Type | — | 484-Ball FCBGA |
| Package Code | — | BGA, 484 balls, Fine-pitch |
| Package Shape | — | Square |
| Terminal Form | — | Ball |
| Temperature Grade | — | Industrial |
| Tension d'alimentation | — | 1.5 V core / 3.3 V aux (per Mercury datasheet) |
| Clock Management | — | PLLs (per Mercury family) |
| Boundary-Scan | — | IEEE 1149.1 / JTAG |