EP1S20B672C7N vs EP1S25B672C7 Comparación
Comparación detallada lado a lado de EP1S20B672C7N por Intel y EP1S25B672C7 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1S20B672C7N | EP1S25B672C7 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $320,00 | $175,00 |
| Series | Stratix | — |
| Family | Stratix (original) | Stratix |
| Process Technology | 0.13 µm CMOS | 130 nm CMOS |
| Logic Elements (LEs) | 18,460 | — |
| LABs / CLBs | 1,846 | — |
| Embedded Memory Bits | 1,669,248 bits | — |
| Maximum User I/O | 426 | 473 |
| Number of Pins / Balls | 672 | — |
| Package Type | 672-BBGA (Fine-pitch BGA, 35 × 35 mm, 1.27 mm pitch) | — |
| Supply Voltage (Core, VCCINT) | 1.5 V | — |
| Temperatura de funcionamiento | 0 °C to 85 °C (Commercial Extended) | 0 C to 85 C |
| Speed Grade | -7 | C7 (commercial, slowest bin) |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount |
| Nivel MSL | 3 (per JEDEC J-STD-020) | — |
| Logic Family | CMOS | CMOS |
| Estado RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Logic Cells | — | 25,660 |
| Logic Array Blocks (LABs) | — | 2,566 |
| Embedded Memory (bits) | — | 1,944,576 |
| Core Voltage | — | 1.5 V |
| Maximum Internal Frequency | — | 420.17 MHz |
| Number of PLLs | — | [DATA_NEEDED: PLL count] |
| Encapsulado | — | 672-BGA, 35 x 35 mm, 1.27 mm pitch |
| Recuento de pines | — | 672 |
| Configuration Method | — | SRAM-based (volatile, requires config device) |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |