EP1S25F672C5N vs EP1S25F672C8 Comparación
Comparación detallada lado a lado de EP1S25F672C5N por Intel y EP1S25F672C8 por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP1S25F672C5N | EP1S25F672C8 |
|---|---|---|
| Marca | Intel | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $142,00 | $525,00 |
| Family | Stratix | Stratix |
| Series | EP1S25 | — |
| Logic Elements (Cells) | 25,660 | — |
| Number of CLBs | 2,566 | — |
| Number of Logic Cells / Gates | [DATA_NEEDED: total system gates] | — |
| Process Technology | 130 nm CMOS | 130 nm CMOS |
| Maximum Internal Frequency | 500 MHz | — |
| Core Supply Voltage | 1.5 V (nominal) | 1.5 V |
| Number of I/O Pins | 473 user I/O | — |
| Number of I/O Banks | [DATA_NEEDED: I/O bank count] | — |
| Package Type | FineLine BGA (FBGA) | — |
| Package Pin Count | 672 | — |
| Ball Pitch | 1.00 mm | — |
| Rango de temperatura de funcionamiento | 0 °C to +85 °C (commercial) | — |
| Speed Grade | C5 | C8 (commercial, -8) |
| Lead-Free (Pb-Free) | Yes (suffix "N") | — |
| Configuration Method | SRAM-based, programmable via JTAG / Passive Serial / Fast Passive Parallel | JTAG / Altera configuration device |
| Tipo de montaje | Surface Mount (BGA) | Surface Mount |
| Estado RoHS | Compliant | [DATA_NEEDED: RoHS Status] |
| Logic Elements | — | 25,660 |
| Logic Array Blocks (LABs) | — | 2,566 |
| User I/Os | — | 473 |
| Maximum Operating Frequency | — | 357.14 MHz |
| Encapsulado | — | 672-ball FineLine BGA (FBGA) |
| Package Dimensions | — | 35 x 35 mm, 1.27 mm pitch |
| Temperatura de funcionamiento | — | 0 C to +85 C (commercial) |
| Nivel MSL | — | [DATA_NEEDED: MSL Level] |
| Logic Family | — | CMOS |