EP1SGX25FF1020I6N vs EP1SGX25FF1020I7 Comparación
Comparación detallada lado a lado de EP1SGX25FF1020I6N por Altera y EP1SGX25FF1020I7 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Altera
EP1SGX25FF1020I7 - Stratix GX FPGA 25,660 Cells, 1.5V, FC-FBGA-1020 | Altera / Intel
EP1SGX25FF1020I7 ObsoleteComparación de especificaciones
| Parámetro | EP1SGX25FF1020I6N | EP1SGX25FF1020I7 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $145,00 | $210,00 |
| Manufacturer | Altera (Intel) | — |
| Series | Stratix GX | EP1SGX25 |
| Family | Stratix GX FPGA | Stratix GX |
| Logic Elements (LE) | 25,660 | — |
| Number of LABs/CLBs | 2,566 | — |
| Total RAM Bits | 1,944,576 | — |
| User I/O Count | 607 | — |
| Supply Voltage - Core | 1.425 V to 1.575 V | — |
| Temperatura de funcionamiento | -40 °C to +100 °C (Industrial) | — |
| Tipo de montaje | Surface Mount | Surface Mount (FC-FBGA) |
| Encapsulado / Carcasa | 1020-BBGA, FCBGA | — |
| Supplier Device Package | 1020-FBGA (33x33) | — |
| Speed Grade | 6 | 7 (highest production grade) |
| Process Node | 0.13 µm | — |
| Embedded Transceivers | Stratix GX multi-gigabit transceivers (MGTs) | Yes (Stratix GX feature) |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Logic Cells | — | 25,660 |
| Configurable Logic Blocks (CLBs) | — | 2,566 |
| Process Technology | — | 130 nm CMOS |
| Core Supply Voltage | — | 1.5 V |
| Encapsulado | — | FC-FBGA-1020 (Flip-Chip Fine-pitch BGA) |
| Number of Terminals / Balls | — | 1020 |
| Terminal Form | — | Ball |
| Temperature Grade (suffix 'I') | — | Industrial |
| Terminal Pitch | — | [DATA_NEEDED: terminal pitch] |
| Combinatorial Delay per CLB | — | 9.48 ns (per Microchip USA listing) |
| Combinatorial Delay Variant | — | [DATA_NEEDED: tPD per CLB variant speed grade] |
| Maximum Internal Clock Frequency | — | [DATA_NEEDED: max Fmax in MHz per speed grade] |
| Configuration Method | — | SRAM-based (volatile, requires configuration at power-up) |
| Nivel MSL | — | [DATA_NEEDED: MSL level] |