EP1SGX25FF1020I6N vs EP1SGX25FF1020I7 对比

详细并排对比 EP1SGX25FF1020I6N 出自 Altera 和 EP1SGX25FF1020I7 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EP1SGX25FF1020I6N EP1SGX25FF1020I7
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $145.00 $210.00
Manufacturer Altera (Intel) —
Series Stratix GX EP1SGX25
Family Stratix GX FPGA Stratix GX
Logic Elements (LE) 25,660 —
Number of LABs/CLBs 2,566 —
Total RAM Bits 1,944,576 —
User I/O Count 607 —
Supply Voltage - Core 1.425 V to 1.575 V —
工作温度 -40 °C to +100 °C (Industrial) —
安装类型 Surface Mount Surface Mount (FC-FBGA)
封装 / 外壳 1020-BBGA, FCBGA —
Supplier Device Package 1020-FBGA (33x33) —
Speed Grade 6 7 (highest production grade)
Process Node 0.13 µm —
Embedded Transceivers Stratix GX multi-gigabit transceivers (MGTs) Yes (Stratix GX feature)
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance]
Logic Cells — 25,660
Configurable Logic Blocks (CLBs) — 2,566
Process Technology — 130 nm CMOS
Core Supply Voltage — 1.5 V
封装 — FC-FBGA-1020 (Flip-Chip Fine-pitch BGA)
Number of Terminals / Balls — 1020
Terminal Form — Ball
Temperature Grade (suffix 'I') — Industrial
Terminal Pitch — [DATA_NEEDED: terminal pitch]
Combinatorial Delay per CLB — 9.48 ns (per Microchip USA listing)
Combinatorial Delay Variant — [DATA_NEEDED: tPD per CLB variant speed grade]
Maximum Internal Clock Frequency — [DATA_NEEDED: max Fmax in MHz per speed grade]
Configuration Method — SRAM-based (volatile, requires configuration at power-up)
MSL 等级 — [DATA_NEEDED: MSL level]

数据手册与资源

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