EP610DC35 vs EP610DC-35 Comparación
Comparación detallada lado a lado de EP610DC35 por Altera y EP610DC-35 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP610DC35 | EP610DC-35 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $19,20 | $18,40 |
| Family | Classic EPLD | Altera Classic EP610 |
| Logic Elements | 16 macrocells | — |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 35 ns | 35 ns |
| Maximum Frequency | 28.6 MHz | — |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| Tensión de alimentación | 5 V | — |
| Encapsulado | 24-pin CDIP (Ceramic DIP) with quartz erase window | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| Tipo de montaje | Through-Hole | Through-Hole (DIP) |
| Recuento de pines | 24 | — |
| Technology | UV-erasable CMOS EPROM | — |
| Programming Method | Altera legacy programmer (PLDLMax or compatible) | — |
| Temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| I/O Pins | [DATA_NEEDED: number of user I/O pins] | — |
| Device Type | — | CPLD - Classic EPLD |
| Macrocells | — | 16 |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Process Technology | — | CMOS |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| Manufacturer | — | Originally Altera; today supplied via Rochester Electronics (authorized) |