EP610DC35 vs EP610DC-35 Comparaison
Comparaison détaillée côte à côte de EP610DC35 par Altera et EP610DC-35 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EP610DC35 | EP610DC-35 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $19,20 | $18,40 |
| Family | Classic EPLD | Altera Classic EP610 |
| Logic Elements | 16 macrocells | — |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 35 ns | 35 ns |
| Maximum Frequency | 28.6 MHz | — |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| Tension d'alimentation | 5 V | — |
| Boîtier | 24-pin CDIP (Ceramic DIP) with quartz erase window | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| Type de montage | Through-Hole | Through-Hole (DIP) |
| Nombre de broches | 24 | — |
| Technology | UV-erasable CMOS EPROM | — |
| Programming Method | Altera legacy programmer (PLDLMax or compatible) | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| I/O Pins | [DATA_NEEDED: number of user I/O pins] | — |
| Device Type | — | CPLD - Classic EPLD |
| Macrocells | — | 16 |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Process Technology | — | CMOS |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| Manufacturer | — | Originally Altera; today supplied via Rochester Electronics (authorized) |