EP610DC35 vs EP610DC-35 비교
다음의 상세 나란히 비교: EP610DC35 제조: Altera 및 EP610DC-35 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP610DC35 | EP610DC-35 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | NRND |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $19.20 | $18.40 |
| Family | Classic EPLD | Altera Classic EP610 |
| Logic Elements | 16 macrocells | — |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 35 ns | 35 ns |
| Maximum Frequency | 28.6 MHz | — |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| 공급 전압 | 5 V | — |
| 패키지 | 24-pin CDIP (Ceramic DIP) with quartz erase window | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| 실장 유형 | Through-Hole | Through-Hole (DIP) |
| 핀 수 | 24 | — |
| Technology | UV-erasable CMOS EPROM | — |
| Programming Method | Altera legacy programmer (PLDLMax or compatible) | — |
| 동작 온도 | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| RoHS 상태 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| I/O Pins | [DATA_NEEDED: number of user I/O pins] | — |
| Device Type | — | CPLD - Classic EPLD |
| Macrocells | — | 16 |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Process Technology | — | CMOS |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| Manufacturer | — | Originally Altera; today supplied via Rochester Electronics (authorized) |