EP610DC35 vs EP610DC-35 对比
详细并排对比 EP610DC35 出自 Altera 和 EP610DC-35 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EP610DC35 | EP610DC-35 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 不推荐新设计 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $19.20 | $18.40 |
| Family | Classic EPLD | Altera Classic EP610 |
| Logic Elements | 16 macrocells | — |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 35 ns | 35 ns |
| Maximum Frequency | 28.6 MHz | — |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| 电源电压 | 5 V | — |
| 封装 | 24-pin CDIP (Ceramic DIP) with quartz erase window | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| 安装类型 | Through-Hole | Through-Hole (DIP) |
| 引脚数量 | 24 | — |
| Technology | UV-erasable CMOS EPROM | — |
| Programming Method | Altera legacy programmer (PLDLMax or compatible) | — |
| 工作温度 | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| RoHS 状态 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| I/O Pins | [DATA_NEEDED: number of user I/O pins] | — |
| Device Type | — | CPLD - Classic EPLD |
| Macrocells | — | 16 |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Process Technology | — | CMOS |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| Manufacturer | — | Originally Altera; today supplied via Rochester Electronics (authorized) |