EP910DC-30 vs EP910DC-40 Comparación
Comparación detallada lado a lado de EP910DC-30 por Intel y EP910DC-40 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910DC-30 | EP910DC-40 |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $15,60 | $13,95 |
| Family | Classic EPLD (EP910 series) | — |
| Architecture | PAL-type AND-OR sum-of-products, CMOS | PAL-type AND/OR, UV-erasable CMOS |
| Gate Count | 900 usable gates | — |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 30 ns (max) | — |
| Clock Frequency (fCNT) | 33.3 MHz | — |
| Dedicated Inputs | 36 | 12 |
| Outputs (Macrocells) | 24 | — |
| External Clock Pins | 2 (CLK1, CLK2) | — |
| Tensión de alimentación | 5 V | 5 V (typical for Classic EPLD family) |
| Process Technology | CMOS | — |
| Programming Method | UV-Erasable / OTP | UV-erase + EPROM programmer; on-board logic test circuitry |
| Encapsulado | DIP-40 (through-hole, 600 mil) | DIP-40 (ceramic, through-hole) |
| Temperatura de funcionamiento | 0C to +70C (commercial) | — |
| Tipo de montaje | Through-Hole | Through-Hole |
| Device Family | — | Classic EPLD (EP910 series) |
| Bidirectional I/O Pins | — | 24 |
| Total Inputs to Logic Array | — | 36 |
| Product Terms | — | 240 maximum |
| Maximum Propagation Delay (tPD) | — | 40 ns |
| Maximum Operating Frequency (fMAX) | — | 25 MHz |
| Global Clocks | — | 2 |
| Operating Temperature (Commercial) | — | 0 °C to 70 °C |
| Estado RoHS | — | [DATA_NEEDED: rohs_status] |