EP910DC-30 vs EP910DC-40 比較
詳細並排比較 EP910DC-30 由 Intel 與 EP910DC-40 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910DC-30 | EP910DC-40 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Classic EPLD (EP910 series) | — |
| Architecture | PAL-type AND-OR sum-of-products, CMOS | PAL-type AND/OR, UV-erasable CMOS |
| Gate Count | 900 usable gates | — |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 30 ns (max) | — |
| Clock Frequency (fCNT) | 33.3 MHz | — |
| Dedicated Inputs | 36 | 12 |
| Outputs (Macrocells) | 24 | — |
| External Clock Pins | 2 (CLK1, CLK2) | — |
| 供應電壓 | 5 V | 5 V (typical for Classic EPLD family) |
| Process Technology | CMOS | — |
| Programming Method | UV-Erasable / OTP | UV-erase + EPROM programmer; on-board logic test circuitry |
| 封裝 | DIP-40 (through-hole, 600 mil) | DIP-40 (ceramic, through-hole) |
| 工作溫度 | 0C to +70C (commercial) | — |
| 安裝類型 | Through-Hole | Through-Hole |
| Device Family | — | Classic EPLD (EP910 series) |
| Bidirectional I/O Pins | — | 24 |
| Total Inputs to Logic Array | — | 36 |
| Product Terms | — | 240 maximum |
| Maximum Propagation Delay (tPD) | — | 40 ns |
| Maximum Operating Frequency (fMAX) | — | 25 MHz |
| Global Clocks | — | 2 |
| Operating Temperature (Commercial) | — | 0 °C to 70 °C |
| RoHS 狀態 | — | [DATA_NEEDED: rohs_status] |