EP910DC-30 vs EP910DC-40 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910DC-30 sa pamamagitan ng Intel at EP910DC-40 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910DC-30 | EP910DC-40 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Classic EPLD (EP910 series) | — |
| Architecture | PAL-type AND-OR sum-of-products, CMOS | PAL-type AND/OR, UV-erasable CMOS |
| Gate Count | 900 usable gates | — |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 30 ns (max) | — |
| Clock Frequency (fCNT) | 33.3 MHz | — |
| Dedicated Inputs | 36 | 12 |
| Outputs (Macrocells) | 24 | — |
| External Clock Pins | 2 (CLK1, CLK2) | — |
| Volte ng Pagbibigay | 5 V | 5 V (typical for Classic EPLD family) |
| Process Technology | CMOS | — |
| Programming Method | UV-Erasable / OTP | UV-erase + EPROM programmer; on-board logic test circuitry |
| Packhaging | DIP-40 (through-hole, 600 mil) | DIP-40 (ceramic, through-hole) |
| Temperature na Operasyon | 0C to +70C (commercial) | — |
| Uri ng Pagpapasok | Through-Hole | Through-Hole |
| Device Family | — | Classic EPLD (EP910 series) |
| Bidirectional I/O Pins | — | 24 |
| Total Inputs to Logic Array | — | 36 |
| Product Terms | — | 240 maximum |
| Maximum Propagation Delay (tPD) | — | 40 ns |
| Maximum Operating Frequency (fMAX) | — | 25 MHz |
| Global Clocks | — | 2 |
| Operating Temperature (Commercial) | — | 0 °C to 70 °C |
| Tindminan RoHS | — | [DATA_NEEDED: rohs_status] |