EP910DI-30 vs EP910IDI-15 Comparación
Comparación detallada lado a lado de EP910DI-30 por Rochester Electronics y EP910IDI-15 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Rochester Electronics
EP910DI-30 - 24-Macrocell EPLD, 30ns, CDIP-40 | Altera (Rochester)
EP910DI-30 NrndComparación de especificaciones
| Parámetro | EP910DI-30 | EP910IDI-15 |
|---|---|---|
| Marca | Rochester Electronics | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | NRND | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $17,60 | $29,00 |
| Product Type | UV-Erasable Programmable Logic Device (EPLD) | — |
| Family | Classic EPLD (Altera EP910 series) | Classic EPLD |
| Macrocell Count | 24 | — |
| Propagation Delay (tpd) | 30 ns | — |
| Maximum Toggle Frequency (fmax) | 62 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| Technology | CMOS, UV-erasable EPROM | CMOS EPROM |
| Encapsulado | CDIP-40 (ceramic DIP, 40-pin with UV window) | 40-pin CDIP (CerDIP) with quartz window |
| Tipo de montaje | Through-Hole (DIP) | Through-hole (DIP) |
| Dedicated Inputs | 10 | — |
| Dedicated I/O Pins | 12 (12 input + 12 output) | — |
| Output Enable Pins | 2 | — |
| Recuento de pines | 40 | — |
| Programmable Logic Element | JEDEC fuse map (3rd-party programmer) | — |
| Temperatura de funcionamiento | -40C to +85C (industrial) | -40C to +85C (industrial, "I" grade) |
| Estado RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance of CDIP windowed part] |
| Manufacturer (Original) | Altera (now Intel PSG) | — |
| Current Distributor / Authorized Aftermarket | Rochester Electronics, LLC | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Gates | — | 450 gates |
| Macrocells | — | 24 |
| Maximum User I/O Pins | — | 36 |
| Pin-to-Pin Propagation Delay (tpd) | — | 15 ns |
| Maximum Counter Frequency | — | 66.6 MHz |
| Supply Voltage (Vcc) | — | 5 V |
| Program/Erase Method | — | UV-erasable windowed CerDIP |
| Macrocells Configurable As | — | D, T, JK, SR flip-flop, or combinatorial |
| Development Tool | — | MAX+PLUS II (legacy) / Altera Classic compiler |
| Programming Hardware | — | Altera Logic Programmer card |
| Logic Family Compatibility | — | Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages |