EP910DI-30 vs EP910IDI-15 Comparison
Detailed side-by-side comparison of EP910DI-30 by Rochester Electronics and EP910IDI-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Rochester Electronics
EP910DI-30
EP910DI-30 - 24-Macrocell EPLD, 30ns, CDIP-40 | Altera (Rochester)
EP910DI-30 NrndAltera
EP910IDI-15
EP910IDI-15 - 24-Macrocell Classic EPLD 15ns | Intel / Altera
EP910IDI-15 ObsoleteSpecification Comparison
| Parameter | EP910DI-30 | EP910IDI-15 |
|---|---|---|
| Brand | Rochester Electronics | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.60 | $29.00 |
| Product Type | UV-Erasable Programmable Logic Device (EPLD) | β |
| Family | Classic EPLD (Altera EP910 series) | Classic EPLD |
| Macrocell Count | 24 | β |
| Propagation Delay (tpd) | 30 ns | β |
| Maximum Toggle Frequency (fmax) | 62 MHz | β |
| Supply Voltage (VCC) | 5 V (single supply) | β |
| Technology | CMOS, UV-erasable EPROM | CMOS EPROM |
| Package | CDIP-40 (ceramic DIP, 40-pin with UV window) | 40-pin CDIP (CerDIP) with quartz window |
| Mounting Type | Through-Hole (DIP) | Through-hole (DIP) |
| Dedicated Inputs | 10 | β |
| Dedicated I/O Pins | 12 (12 input + 12 output) | β |
| Output Enable Pins | 2 | β |
| Pin Count | 40 | β |
| Programmable Logic Element | JEDEC fuse map (3rd-party programmer) | β |
| Operating Temperature | -40C to +85C (industrial) | -40C to +85C (industrial, "I" grade) |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance of CDIP windowed part] |
| Manufacturer (Original) | Altera (now Intel PSG) | β |
| Current Distributor / Authorized Aftermarket | Rochester Electronics, LLC | β |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Logic Gates | β | 450 gates |
| Macrocells | β | 24 |
| Maximum User I/O Pins | β | 36 |
| Pin-to-Pin Propagation Delay (tpd) | β | 15 ns |
| Maximum Counter Frequency | β | 66.6 MHz |
| Supply Voltage (Vcc) | β | 5 V |
| Program/Erase Method | β | UV-erasable windowed CerDIP |
| Macrocells Configurable As | β | D, T, JK, SR flip-flop, or combinatorial |
| Development Tool | β | MAX+PLUS II (legacy) / Altera Classic compiler |
| Programming Hardware | β | Altera Logic Programmer card |
| Logic Family Compatibility | β | Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages |