EP910DI-30 vs EP910IDI-15 비교

다음의 상세 나란히 비교: EP910DI-30 제조: Rochester Electronics 및 EP910IDI-15 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EP910DI-30 EP910IDI-15
브랜드 Rochester Electronics Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 NRND Obsolete
재고 상태 In Stock In Stock
단가 (USD) $17.60 $29.00
Product Type UV-Erasable Programmable Logic Device (EPLD) —
Family Classic EPLD (Altera EP910 series) Classic EPLD
Macrocell Count 24 —
Propagation Delay (tpd) 30 ns —
Maximum Toggle Frequency (fmax) 62 MHz —
Supply Voltage (VCC) 5 V (single supply) —
Technology CMOS, UV-erasable EPROM CMOS EPROM
패키지 CDIP-40 (ceramic DIP, 40-pin with UV window) 40-pin CDIP (CerDIP) with quartz window
실장 유형 Through-Hole (DIP) Through-hole (DIP)
Dedicated Inputs 10 —
Dedicated I/O Pins 12 (12 input + 12 output) —
Output Enable Pins 2 —
핀 수 40 —
Programmable Logic Element JEDEC fuse map (3rd-party programmer) —
동작 온도 -40C to +85C (industrial) -40C to +85C (industrial, "I" grade)
RoHS 상태 [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance of CDIP windowed part]
Manufacturer (Original) Altera (now Intel PSG) —
Current Distributor / Authorized Aftermarket Rochester Electronics, LLC —
Device Type — CPLD (Complex Programmable Logic Device)
Logic Gates — 450 gates
Macrocells — 24
Maximum User I/O Pins — 36
Pin-to-Pin Propagation Delay (tpd) — 15 ns
Maximum Counter Frequency — 66.6 MHz
Supply Voltage (Vcc) — 5 V
Program/Erase Method — UV-erasable windowed CerDIP
Macrocells Configurable As — D, T, JK, SR flip-flop, or combinatorial
Development Tool — MAX+PLUS II (legacy) / Altera Classic compiler
Programming Hardware — Altera Logic Programmer card
Logic Family Compatibility — Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages

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