EP910LC-32 vs EP910LC-40 Comparación
Comparación detallada lado a lado de EP910LC-32 por Altera y EP910LC-40 por Rochester Electronics. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Rochester Electronics
EP910LC-40 - 450-Gate CMOS EPLD, 40ns, PQCC-44 | Rochester / Altera
EP910LC-40 ObsoleteComparación de especificaciones
| Parámetro | EP910LC-32 | EP910LC-40 |
|---|---|---|
| Marca | Altera | Rochester Electronics |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $9,85 | $52,00 |
| Device Family | Altera Classic EPLD | Altera Classic EPLD - EP910 |
| Number of Macrocells | 24 | — |
| Number of Usable Gates | 900 gates (typical) | — |
| Number of Dedicated Inputs | 10 | — |
| Number of I/O Pins | 20 | — |
| Encapsulado | PLCC-32 | PQCC-44 (Plastic Leaded Chip Carrier, J-lead) |
| Speed Grade | -32 | — |
| Maximum Toggle Frequency (fMAX) | [DATA_NEEDED: fMAX value in MHz for -32 grade] | 25 MHz |
| Pin-to-Pin Propagation Delay (tPD) | [DATA_NEEDED: tPD in ns for -32 grade] | — |
| Supply Voltage (VCC) | 5 V | 5 V (single supply) |
| Logic Family | Low-power CMOS (LC suffix) | — |
| Programming Method | UV-erasable or one-time programmable (OTP for LC windowless variant) | Altera Logic Programmer (PLAD-J), 4-wire serial |
| Rango de temperatura de funcionamiento | [DATA_NEEDED: commercial or industrial grade] | — |
| I/O Standard | TTL-compatible | — |
| Tipo de montaje | Surface Mount (PLCC socket or direct solder) | — |
| Estado RoHS | unknown | Not applicable (legacy) |
| Nivel MSL | unknown | — |
| Manufacturer | — | Rochester Electronics (Altera original) |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 450 |
| Macrocells | — | 24 |
| Logic Array Blocks | — | 2 (12 macrocells each) |
| Propagation Delay (tPD) | — | 40 ns |
| User I/O Pins | — | 36 |
| Dedicated Inputs | — | 4 |
| Technology | — | CMOS EPROM |
| Operating Temperature (Commercial) | — | 0 C to +70 C |
| Lead-Free Status | — | Not applicable |