EP910PI-15T vs EP910PC-20T 比較

詳細な並列比較: EP910PI-15T メーカー: Altera および EP910PC-20T メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EP910PI-15T EP910PC-20T
ブランド Altera Altera
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 Obsolete Unknown
在庫状況 In Stock In Stock
単価(USD) $10.95 $8.70
Product Type Classic EPLD (Erasable Programmable Logic Device) —
Family Altera Classic EPLD (EP910 series) Classic EPLD
Macrocells 24 —
Dedicated Inputs 12 —
I/O Pins 24 —
Logic Blocks 6 LABs of 4 macrocells each (Classic architecture) —
電源電圧 4.5 V to 5.5 V (5 V nominal) [DATA_NEEDED: operating supply voltage]
Propagation Delay (tPD) 15 ns max (speed grade -15) —
Technology CMOS EEPROM (electrically erasable) —
パッケージ 40-pin PDIP (Plastic DIP, R-PDIP-T40) —
実装タイプ Through-Hole —
Output Drive Current [DATA_NEEDED: per-pin DC output current, mA] —
動作温度 [DATA_NEEDED: industrial/commercial temp range] [DATA_NEEDED: operating temperature range]
Programming JEDEC-standard, serial/parallel programmer —
RoHS ステータス [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] unknown
Device Type — EPLD
Fabrication Technology — CMOS
Logic Integration — 300 to 900 usable gates
Logic Emulation — 100% TTL emulation
Application Function — High-speed, low-power logic integration
Programmable Device Class — Erasable programmable logic device
Device Family — Altera Classic EPLD Family
Speed Grade — 20 ns
Package Code — PC
Package Pin Count — [DATA_NEEDED: package pin count]
Package Dimensions — [DATA_NEEDED: package dimensions]
I/O Count — [DATA_NEEDED: I/O count]
Internal Logic Capacity — 300 to 900 usable gates
Supported Logic Integration — Multiple PAL- and GAL-type devices
Programming Interface — [DATA_NEEDED: programming interface]
Programming Voltage — [DATA_NEEDED: programming voltage]
Mounting Technology — [DATA_NEEDED: mounting technology]
REACH Status — unknown
AEC-Q100 Qualification — not_applicable
Lead-Free Status — unknown
Halogen-Free Status — unknown

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