EP910PI-30T vs EP910PI-40 Comparación
Comparación detallada lado a lado de EP910PI-30T por Altera y EP910PI-40 por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EP910PI-30T | EP910PI-40 |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Última compra |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $10,95 | $9,85 |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD | — |
| Macrocells | 24 | — |
| Usable Gates | 480 | — |
| Dedicated Inputs | 10 | — |
| Propagation Delay (tPD) | 30 ns | 43 ns |
| Register (Clock-to-Output) Delay | 20 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 4.75 V to 5.25 V (5 V nominal) |
| Technology | CMOS, UV-erasable (windowed ceramic) | — |
| Package Type | 40-pin PDIP (ceramic windowed) | — |
| Tipo de montaje | Through-Hole | Through-Hole |
| Temperatura de funcionamiento | -40 C to +85 C (industrial) | 0C to +70C (commercial) |
| Programming | Altera Classic device programmer / MAX+PLUS II flow | — |
| Estado RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Family | — | Classic EPLD |
| Part Number | — | EP910PI-40 |
| Architecture | — | PAL-type macrocell, CMOS, UV-erasable |
| Number of Macrocells | — | 24 |
| Number of Dedicated Inputs | — | 12 |
| Number of I/O Lines | — | 24 |
| External Clock Inputs | — | 2 |
| Frecuencia de reloj máxima | — | 25 MHz |
| Speed Grade | — | -40 (43 ns) |
| Encapsulado | — | PDIP-40 (Plastic DIP, 40-pin) |
| Process Technology | — | CMOS (UV-erasable) |
| Programming Method | — | UV-erase + Altera programmer (legacy) |
| Programmable Polarity | — | Yes (user-configurable output) |
| Output Enable Control | — | Yes (per-pin three-state) |