EP910PI-30T vs EP910PI-40 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910PI-30T sa pamamagitan ng Altera at EP910PI-40 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910PI-30T EP910PI-40
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Huling Pagbili
Product Type EPLD (Erasable Programmable Logic Device) —
Family Altera Classic EPLD —
Macrocells 24 —
Usable Gates 480 —
Dedicated Inputs 10 —
Propagation Delay (tPD) 30 ns 43 ns
Register (Clock-to-Output) Delay 20 ns —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 4.75 V to 5.25 V (5 V nominal)
Technology CMOS, UV-erasable (windowed ceramic) —
Package Type 40-pin PDIP (ceramic windowed) —
Uri ng Pagpapasok Through-Hole Through-Hole
Temperature na Operasyon -40 C to +85 C (industrial) 0C to +70C (commercial)
Programming Altera Classic device programmer / MAX+PLUS II flow —
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Lead-Free [DATA_NEEDED: lead-free status] —
Device Family — Classic EPLD
Part Number — EP910PI-40
Architecture — PAL-type macrocell, CMOS, UV-erasable
Number of Macrocells — 24
Number of Dedicated Inputs — 12
Number of I/O Lines — 24
External Clock Inputs — 2
Maksimum na Taktiko ng Oras — 25 MHz
Speed Grade — -40 (43 ns)
Packhaging — PDIP-40 (Plastic DIP, 40-pin)
Process Technology — CMOS (UV-erasable)
Programming Method — UV-erase + Altera programmer (legacy)
Programmable Polarity — Yes (user-configurable output)
Output Enable Control — Yes (per-pin three-state)

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